Hironori Yamauchi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
5
Active years
1985–2006
Best venue rank
Multiconference
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | ASPDAC | Configurable multi-processor architecture and its processor element design. | Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi |
| 2006 | ICARCV | Human Behavior Recognition for Daily Task Assistance using Sparse Range Data Observations. | Akira Utsumi, Hirotake Yamazoe, Shinji Abe, Daisuke Kanbara, Hironori Yamauchi |
| 2004 | ISCAS | VLSI processor architecture for real-time GA processing and PE-VLSI design. | Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi |
| 2002 | ICASSP | Scalable GA processor architecture and its implementation of processor-element. | Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi |
| 1991 | ICASSP | A real-time 256256 point two-dimensional FFT single-chip processor. | Hiroshi Miyanaga, Hironori Yamauchi, Kazuhiro Matsuda |
| 1991 | ICASSP | A highly-parallel single-chip DSP architecture for video signal processing. | Hironori Yamauchi, Yutaka Tashiro, Toshihiro Minami, Yutaka Suzuki |
| 1991 | ITC | An Organized Firmware Verification Environment for the Programmable Image DSP. | Yutaka Tashiro, Hironori Yamauchi, Toshihiro Minami, Tetsuo Tajiri, Yutaka Suzuki |
| 1986 | ICASSP | A 50ns floating-point signal processor VLSI. | Takao Kaneko, Hironori Yamauchi, Atsushi Iwata |
| 1985 | ICASSP | An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM. | Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono |