| 2026 | CC | Inside VOLT: Designing an Open-Source GPU Compiler (Tool). | Shinnung Jeong, Chihyo Ahn, Huanzhi Pu, Jisheng Zhao, Hyesoon Kim, Blaise Tine |
| 2026 | ISPASS | Macsim Mini: A Lightweight Cycle-Level GPU Simulator for Architecture Education. | Euijun Chung, Saurabh Singh, Huanzhi Pu, Yuxiao Jia, Anurag Kar, Sam Jijina, Scott Madeira, Hyesoon Kim |
| 2026 | ISPASS | TensorDynamic: Bridging Application- and Instruction-Level Fault Injection for DNN Tensor Core Execution. | Yuxiao Jia, Euijun Chung, Huanzhi Pu, Ben Feinberg, Hyesoon Kim |
| 2026 | PPoPP | Scaling GPU-to-CPU Migration for Efficient Distributed Execution on CPU Clusters. | Ruobing Han, Hyesoon Kim |
| 2025 | FCCM | SoftCUDA: Running CUDA on Softcore GPU. | Chihyo Ahn, Ruobing Han, Udit Subramanya, Jisheng Zhao, Blaise Tine, Hyesoon Kim |
| 2025 | HPCA | SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads. | Shinnung Jeong, Liam Paul Cooper, Ju Min Lee, Heelim Choi, Nicholas Parnenzini, Chihyo Ahn, Yongwoo Lee, Hanjun Kim, Hyesoon Kim |
| 2025 | HPCA | Let-Me-In: (Still) Employing In-pointer Bounds Metadata for Fine-grained GPU Memory Safety. | Jaewon Lee, Euijun Chung, Saurabh Singh, Seonjin Na, Yonghae Kim, Jaekyu Lee, Hyesoon Kim |
| 2025 | ISPASS | Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels. | Martin Troiber, Martin Schulz, Blaise Tine, Hyesoon Kim |
| 2025 | MICRO | Swift and Trustworthy Large-Scale GPU Simulation with Fine-Grained Error Modeling and Hierarchical Clustering. | Euijun Chung, Seonjin Na, Sung Ha Kang, Hyesoon Kim |
| 2024 | CC | Exponentially Expanding the Phase-Ordering Search Space via Dormant Information. | Ruobing Han, Hyesoon Kim |
| 2024 | CGO | Enabling Fine-Grained Incremental Builds by Making Compiler Stateful. | Ruobing Han, Jisheng Zhao, Hyesoon Kim |
| 2024 | ISCA | Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs. | Yuan Feng, Seonjin Na, Hyesoon Kim, Hyeran Jeon |
| 2024 | MICRO | Unleashing CPU Potential for Executing GPU Programs Through Compiler/Runtime Optimizations. | Ruobing Han, Jisheng Zhao, Hyesoon Kim |
| 2023 | ASPLOS | Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs. | Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Cooper, Hyesoon Kim |
| 2023 | HPCA | VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. | Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya, Eric Qin, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna |
| 2023 | ISM | EHT-SR: An Entropy-Based Hybrid Approach for Faster Super-Resolution. | Abhilash Dharmavarapu, Stefano Petrangeli, Jiashen Cao, Hyesoon Kim |
| 2023 | PPoPP | CuPBoP: A Framework to Make CUDA Portable. | Ruobing Han, Jun Chen, Bhanu Garg, Jeffrey Young, Jaewoong Sim, Hyesoon Kim |
| 2023 | SC | CuPBoP-AMD: Extending CUDA to AMD Platforms. | Jun Chen, Xule Zhou, Hyesoon Kim |
| 2022 | FPL | Maia: Matrix Inversion Acceleration Near Memory. | Bahar Asgari, Dheeraj Ramchandani, Amaan Marfatia, Hyesoon Kim |
| 2022 | ISCA | Securing GPU via region-based bounds checking. | Jaewon Lee, Yonghae Kim, Jiashen Cao, Euna Kim, Jaekyu Lee, Hyesoon Kim |
| 2022 | SIGMOD | FiGO: Fine-Grained Query Optimization in Video Analytics. | Jiashen Cao, Karan Sarkar, Ramyad Hadidi, Joy Arulraj, Hyesoon Kim |
| 2021 | ASPLOS | Quantifying the design-space tradeoffs in autonomous drones. | Ramyad Hadidi, Bahar Asgari, Sam Jijina, Adriana Amyette, Nima Shoghi, Hyesoon Kim |
| 2021 | DAC | RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. | Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna |
| 2021 | HPCA | FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction. | Bahar Asgari, Ramyad Hadidi, Jiashen Cao, Da Eun Shim, Sung Kyu Lim, Hyesoon Kim |
| 2021 | MICRO | Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics. | Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, Hyesoon Kim |
| 2020 | ASPLOS | Batch-Aware Unified Memory Management in GPUs for Irregular Workloads. | Hyojong Kim, Jaewoong Sim, Prasun Gera, Ramyad Hadidi, Hyesoon Kim |
| 2020 | DAC | PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra. | Bahar Asgari, Ramyad Hadidi, Nima Shoghi Ghaleshahi, Hyesoon Kim |
| 2020 | DATE | ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory. | Bahar Asgari, Ramyad Hadidi, Hyesoon Kim |
| 2020 | DATE | Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. | Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim |
| 2020 | FCCM | Proposing a Fast and Scalable Systolic Array for Matrix Multiplication. | Bahar Asgari, Ramyad Hadidi, Hyesoon Kim |
| 2020 | FPGA | Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping. | Blaise Tine, Fares Elsabbagh, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim |
| 2020 | FPGA | Productive Hardware Designs using Hybrid HLS-RTL Development. | Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim |
| 2020 | FPL | RISC-V FPGA Platform Toward ROS-Based Robotics Application. | Jaewon Lee, Hanning Chen, Jeffrey S. Young, Hyesoon Kim |
| 2020 | HPCA | ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. | Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili |
| 2020 | ICCD | MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture. | Bahar Asgari, Ramyad Hadidi, Hyesoon Kim |
| 2020 | ISPASS | Understanding the Software and Hardware Stacks of a General-Purpose Cognitive Drone. | Sam Jijina, Adriana Amyette, Nima Shoghi Ghaleshahi, Ramyad Hadidi, Hyesoon Kim |
| 2020 | MICRO | Hardware-based Always-On Heap Memory Safety. | Yonghae Kim, Jaekyu Lee, Hyesoon Kim |
| 2019 | CGO | Translating CUDA to OpenCL for Hardware Generation using Neural Machine Translation. | Yonghae Kim, Hyesoon Kim |
| 2019 | DAC | LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays. | Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili |
| 2019 | DAC | Robustly Executing DNNs in IoT Systems Using Coded Distributed Computing. | Ramyad Hadidi, Jiashen Cao, Michael S. Ryoo, Hyesoon Kim |
| 2019 | DAC | FlashGPU: Placing New Flash Next to GPU Cores. | Jie Zhang, Miryeong Kwon, Hyojong Kim, Hyesoon Kim, Myoungsoo Jung |
| 2019 | FPL | Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs. | Younmin Bae, Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Hyesoon Kim |
| 2019 | ISPASS | Empirical Investigation of Stale Value Tolerance on Parallel RNN Training. | Joo Hwan Lee, Hyesoon Kim |
| 2018 | ASPLOS | Real-Time Image Recognition Using Collaborative IoT Devices. | Ramyad Hadidi, Jiashen Cao, Matthew Woodward, Michael S. Ryoo, Hyesoon Kim |
| 2018 | ISPASS | Performance Characterisation and Simulation of Intel's Integrated GPU Architecture. | Prasun Gera, Hyojong Kim, Hyesoon Kim, Sunpyo Hong, Vinod George, Chi-Keung Luk |
| 2018 | ISPASS | Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube. | Ramyad Hadidi, Bahar Asgari, Jeffrey S. Young, Burhan Ahmad Mudassar, Kartikay Garg, Tushar Krishna, Hyesoon Kim |
| 2017 | HPCA | GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks. | Lifeng Nai, Ramyad Hadidi, Jaewoong Sim, Hyojong Kim, Pranith Kumar, Hyesoon Kim |
| 2015 | SC | GraphBIG: understanding graph computing in the context of industrial solutions. | Lifeng Nai, Yinglong Xia, Ilie Gabriel Tanase, Hyesoon Kim, Ching-Yung Lin |
| 2014 | FCCM | Harmonica: An FPGA-Based Data Parallel Soft Core. | Chad D. Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, Hyesoon Kim |
| 2014 | HPCA | Spare register aware prefetching for graph algorithms on GPUs. | Nagesh B. Lakshminarayana, Hyesoon Kim |
| 2014 | MICRO | GPUMech: GPU Performance Modeling Technique Based on Interval Analysis. | Jen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, Hsien-Hsin S. Lee |
| 2014 | MICRO | Transparent Hardware Management of Stacked DRAM as Part of Memory. | Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim |
| 2014 | SBAC-PAD | Design Space Exploration of Memory Model for Heterogeneous Computing. | Jieun Lim, Hyesoon Kim |
| 2013 | SC | SESH Framework: A Space Exploration Framework for GPU Application and Hardware Codesign. | Joo Hwan Lee, Jiayuan Meng, Hyesoon Kim |
| 2012 | HPCA | TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture. | Jaekyu Lee, Hyesoon Kim |
| 2012 | ISCA | FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion. | Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim |
| 2012 | MICRO | A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. | Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi |
| 2012 | PLDI | Supporting virtual memory in GPGPU without supporting precise exceptions. | Hyesoon Kim |
| 2012 | PLDI | Design space exploration of memory model for heterogeneous computing. | Jieun Lim, Hyesoon Kim |
| 2012 | PPoPP | A performance analysis framework for identifying potential benefits in GPGPU applications. | Jaewoong Sim, Aniruddha Dasgupta, Hyesoon Kim, Richard W. Vuduc |
| 2010 | CASES | Design space exploration of the turbo decoding algorithm on GPUs. | Dongwon Lee, Marilyn Wolf, Hyesoon Kim |
| 2010 | ISCA | An integrated GPU power and performance model. | Sunpyo Hong, Hyesoon Kim |
| 2010 | MICRO | SD3: A Scalable Approach to Dynamic Data-Dependence Profiling. | Minjang Kim, Hyesoon Kim, Chi-Keung Luk |
| 2010 | MICRO | Many-Thread Aware Prefetching Mechanisms for GPGPU Applications. | Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard W. Vuduc |
| 2009 | ISCA | An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness. | Sunpyo Hong, Hyesoon Kim |
| 2009 | MICRO | Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping. | Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim |
| 2009 | SC | Age based scheduling for asymmetric multiprocessors. | Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim |
| 2008 | ASPLOS | Improving the performance of object-oriented languages with dynamic predication of indirect jumps. | Jos A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt |
| 2008 | HPCA | Performance-aware speculation control using wrong path usefulness prediction. | Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt |
| 2008 | ICCD | Understanding performance, power and energy behavior in asymmetric multiprocessors. | Nagesh B. Lakshminarayana, Hyesoon Kim |
| 2007 | CGO | Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. | Hyesoon Kim, Jos A. Joao, Onur Mutlu, Yale N. Patt |
| 2007 | HPCA | Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. | Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt |
| 2007 | ISCA | VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. | Hyesoon Kim, Jos A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn |
| 2006 | CGO | 2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. | Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt |
| 2006 | MICRO | Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. | Hyesoon Kim, Jos A. Joao, Onur Mutlu, Yale N. Patt |
| 2005 | ISCA | Techniques for Efficient Processing in Runahead Execution Engines. | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
| 2005 | MICRO | Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. | Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt |
| 2005 | MICRO | Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
| 2004 | MICRO | Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. | David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt |
| 2004 | SBAC-PAD | Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt |