Imran Wali
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2014–2017
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | DDECS | Towards approximation during test of Integrated Circuits. | Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio |
| 2016 | ETS | A low-cost susceptibility analysis methodology to selectively harden logic circuits. | Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda |
| 2015 | ETS | An effective hybrid fault-tolerant architecture for pipelined cores. | Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard |
| 2015 | IOLTS | Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. | Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda |
| 2014 | DDECS | Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. | Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri |