| 2026 | DIAGRAMS | Diagrams as a Service. | Niklas Rentz, Maximilian Kasperowski, Reinhard von Hanxleden, Klara Modin, Samuel Miksits, Muhammad Afif Ramadhan, Ingo Sander |
| 2025 | DATE | Towards Coherent Semantics: A Quantitatively Typed EDSL for Synchronous System Design. | Rui Chen, Ingo Sander |
| 2025 | FDL | Automating Transformation Strategy via Attributed Graphs for Process Network Parallelization. | Fahimeh Bahrami, Ingo Sander |
| 2025 | SETTA | Synchronous System Design with Quantitative Types. | Rui Chen, Ingo Sander |
| 2024 | FDL | Automatic Parallelization of Embedded Software via Hierarchical Process Network Transformations. | Fahimeh Bahrami, Rodolfo Jordo, Ingo Sander, George Ungureanu |
| 2024 | FDL | A Quantitative Type Approach to Formal Component-Based System Design. | Rui Chen, Ingo Sander |
| 2024 | FDL | Multi-objective preference-free exact design space exploration of static DSP on multicore platforms. | Rodolfo Jordo, Fahimeh Bahrami, Yu Yang, Matthias Becker, Ingo Sander, Kathrin Rosvall |
| 2022 | FDL | A multi-view and programming language agnostic framework for model-driven engineering. | Rodolfo Jordo, Fahimeh Bahrami, Rui Chen, Ingo Sander |
| 2021 | DATE | Formulation of Design Space Exploration Problems by Composable Design Space Identification. | Rodolfo Jordo, Ingo Sander, Matthias Becker |
| 2020 | FDL | Exploiting Dataflow Models for Parallel Simulation of Discrete Timed Systems. | George Ungureanu, Rodolfo Jordo, Ingo Sander |
| 2019 | FDL | Formal Design, Co-Simulation and Validation of a Radar Signal Processing System. | George Ungureanu, Timmy Sundstrm, Anders hlander, Ingo Sander, Ingemar Sderquist |
| 2018 | DATE | An algebra for modeling continuous time systems. | Jos Edil G. de Medeiros, George Ungureanu, Ingo Sander |
| 2018 | DATE | Bridging discrete and continuous time models with atoms. | George Ungureanu, Jos Edil G. de Medeiros, Ingo Sander |
| 2018 | DSD | Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors. | Kathrin Rosvall, Tage Mohammadat, George Ungureanu, Johnny berg, Ingo Sander |
| 2017 | DATE | Automatic construction of models for analytic system-level design space exploration problems. | Seyed-Hosein Attarzadeh-Niaki, Ingo Sander |
| 2017 | DATE | A layered formal framework for modeling of cyber-physical systems. | George Ungureanu, Ingo Sander |
| 2016 | DSD | CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties. | Ralph Grgen, Kim Grttner, Fernando Herrera, Pablo Peil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Ral Valencia, Ingo Sander, Kathrin Rosvall, Davide Quaglia |
| 2016 | DSD | SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems. | Alina Lenz, Mikel Azkarate-Askasua Blazquez, Javier Coronel, Alfons Crespo, Simon Davidmann, Juan Carlos Diaz Garcia, Nera Gonzlez Romero, Kim Grttner, Roman Obermaisser, Johnny berg, Jon Prez, Ingo Sander, Ingemar Sderquist |
| 2016 | FDL | A modular design space exploration framework for multiprocessor real-time systems. | Nima Khalilzad, Kathrin Rosvall, Ingo Sander |
| 2015 | DATE | Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints. | Edoardo Paone, Francesco Robino, Gianluca Palermo, Vittorio Zaccaria, Ingo Sander, Cristina Silvano |
| 2014 | DATE | A constraint-based design space exploration framework for real-time applications on MPSoCs. | Kathrin Rosvall, Ingo Sander |
| 2014 | FDL | Synthesizing code for GPGPUs from abstract formal models. | Gabriel Hjort Blindell, Christian Menne, Ingo Sander |
| 2014 | FDL | An extensible infrastructure for modeling and time analysis of predictable embedded systems. | Fernando Herrera, Ingo Sander |
| 2013 | DATE | The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks. | Byron Navas, Ingo Sander, Johnny berg |
| 2013 | DATE | An automated parallel simulation flow for heterogeneous embedded systems. | Seyed-Hosein Attarzadeh-Niaki, Ingo Sander |
| 2013 | DSD | Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems. | Fernando Herrera, Seyed-Hosein Attarzadeh-Niaki, Ingo Sander |
| 2013 | FDL | Combining analytical and simulation-based design space exploration for time-critical systems. | Fernando Herrera, Ingo Sander |
| 2013 | FDL | Rapid virtual prototyping of real-time systems using predictable platform characterizations. | Seyed-Hosein Attarzadeh-Niaki, Marcus Mikulcak, Ingo Sander |
| 2012 | FDL | Integrating virtual platforms into a heterogeneous MoC-based modeling framework. | Gilmar S. Beserra, Seyed-Hosein Attarzadeh-Niaki, Ingo Sander |
| 2012 | FDL | Formal heterogeneous system modeling with SystemC. | Seyed-Hosein Attarzadeh-Niaki, Mikkel Koefoed Jakobsen, Tero Sulonen, Ingo Sander |
| 2011 | DATE | Predicting bus contention effects on energy and performance in multi-processor SoCs. | Sandro Penolazzi, Ingo Sander, Ahmed Hemani |
| 2011 | FDL | Semi-formal refinement of heterogeneous embedded systems by foreign model integration. | Seyed-Hosein Attarzadeh-Niaki, Ingo Sander |
| 2010 | ASPDAC | Constrained global scheduling of streaming applications on MPSoCs. | Jun Zhu, Ingo Sander, Axel Jantsch |
| 2010 | DATE | Predicting energy and performance overhead of Real-Time Operating Systems. | Sandro Penolazzi, Ingo Sander, Ahmed Hemani |
| 2010 | DATE | Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. | Jun Zhu, Ingo Sander, Axel Jantsch |
| 2010 | FDL | HetMoC: Heterogeneous Modelling in SystemC. | Jun Zhu, Ingo Sander, Axel Jantsch |
| 2009 | DATE | Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. | Jun Zhu, Ingo Sander, Axel Jantsch |
| 2008 | EMSOFT | Energy efficient streaming applications with guaranteed throughput on MPSoCs. | Jun Zhu, Ingo Sander, Axel Jantsch |
| 2007 | FPL | The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. | Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, Florian Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, Marcos Martnez |
| 2007 | RSP | Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. | Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch |
| 2006 | DSD | Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. | Zhonghai Lu, Ingo Sander, Axel Jantsch |
| 2006 | DSD | Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads. | Rikard Thid, Ingo Sander, Axel Jantsch |
| 2005 | ASPDAC | Feasibility analysis of messages for on-chip networks using wormhole routing. | Zhonghai Lu, Axel Jantsch, Ingo Sander |
| 2005 | FDL | Refinement of Perfectly Synchronous Communication Model. | Zhonghai Lu, Ingo Sander, Axel Jantsch |
| 2005 | ICCAD | System level verification of digital signal processing applications based on the polynomial abstraction technique. | Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch |
| 2004 | DATE | Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits. | Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch |
| 2003 | DATE | Development and Application of Design Transformations in ForSyDe. | Ingo Sander, Axel Jantsch, Zhonghai Lu |
| 2002 | DAC | Transformation based communication and clock domain refinement for system design. | Ingo Sander, Axel Jantsch |
| 1999 | VLSID | Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons. | Ingo Sander, Axel Jantsch |