Jagdish C. Rao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
1999–2009
Best venue rank
National
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | VLSID | Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. | R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao |
| 2008 | ISLPED | Clock gating for power optimization in ASIC design cycle theory & practice. | Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao |
| 2002 | VLSID | Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. | Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji |
| 2000 | VLSID | A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. | Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar |
| 1999 | ICCD | A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. | Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G. |
| 1999 | VLSID | A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. | Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar |