Javier Valls
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
13
Venues
6
Active years
1999–2018
Best venue rank
C
Where they publish
Papers
13 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | DSD | High-Throughput One-Channel RS(255, 239) Decoder. | Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Miguel Garcia-Herrero |
| 2015 | ISCAS | A 630 Mbps non-binary LDPC decoder for FPGA. | Jesus Omar Lacruz, Francisco Garcia-Herrero, Ma Jos Canet, Javier Valls, Asuncion Perez-Pascual |
| 2013 | ACSSC | Low latency T-EMS decoder for non-binary LDPC codes. | Erbao Li, Francisco Garcia-Herrero, David Declercq, Kiran K. Gunnam, Jesus Omar Lacruz, Javier Valls |
| 2009 | FPL | FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. | Roberto Gutirrez, Javier Valls, Asuncion Perez-Pascual |
| 2007 | FPL | Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. | Roberto Gutirrez, Javier Valls |
| 2007 | PIMRC | Time Synchronization for the IEEE 802.11a/g WLAN Standard. | Mara Jos Canet, Vicen Almenar, Jos Marn-Roig, Javier Valls |
| 2005 | FPL | Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. | Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls |
| 2005 | FPL | Statistical Power Estimation for FPGA. | Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo |
| 2004 | FPGA | Power analysis and estimation tool integrated with XPOWER. | Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls |
| 2004 | PIMRC | A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. | Ma Jos Canet, Felip Vicedo, Vicen Almenar, Javier Valls, Eduardo R. de Lima |
| 2002 | ISCAS | FPGA-based radix-4 butterflies for HIPERLAN/2. | A. Perez-Pascual, T. Sansaloni, Javier Valls |
| 2000 | ISCAS | FPGA-based digit-serial complex number multiplier-accumulator. | Trinidad Sansaloni, Javier Valls, Keshab K. Parhi |
| 1999 | ISCAS | Fast FPGA-based pipelined digit-serial/parallel multipliers. | Javier Valls, Trini Sansaloni, Marcos Martnez-Peir, Eduardo I. Boemo |