| 2017 | ASPDAC | Feature extraction from design documents to enable rule learning for improving assertion coverage. | Kuo-Kai Hsieh, Sebastian Siatkowski, Li-C. Wang, Wen Chen, Jayanta Bhadra |
| 2017 | DAC | Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery. | Kuo-Kai Hsieh, Li-C. Wang, Wen Chen, Jayanta Bhadra |
| 2017 | DAC | Extensibility in Automotive Security: Current Practice and Challenges: Invited. | Sandip Ray, Wen Chen, Jayanta Bhadra, Mohammad Abdullah Al Faruque |
| 2014 | ICCAD | On application of data mining in functional debug. | Kuo-Kai Hsieh, Wen Chen, Li-C. Wang, Jayanta Bhadra |
| 2013 | DATE | Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step. | Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra |
| 2012 | ASPDAC | An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. | Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra |
| 2012 | ICCAD | Novel test detection to improve simulation efficiency - A commercial experiment. | Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir |
| 2010 | ITC | A kernel-based approach for functional test program generation. | Po-Hsien Chang, Li-C. Wang, Jayanta Bhadra |
| 2010 | VTS | Innovative practices session 7C: Verification and testing challenges in high-level synthesis. | Sandip Ray, Jayanta Bhadra |
| 2009 | ICCAD | On soft error rate analysis of scaled CMOS designs - A statistical perspective. | Huan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra |
| 2009 | ITC | Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning. | Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra |
| 2009 | ITC | Portable simulation/emulation stimulus on an industrial-strength SoC. | Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, Jayanta Bhadra |
| 2007 | FMCAD | A Mechanized Refinement Framework for Analysis of Custom Memories. | Sandip Ray, Jayanta Bhadra |
| 2007 | ICCAD | An incremental learning framework for estimating signal controllability in unit-level verification. | Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra |
| 2007 | ITC | Enhancing signal controllability in functional test-benches through automatic constraint extraction. | Onur Guzey, Li-C. Wang, Jayanta Bhadra |
| 2004 | ITC | Formal Verification of a System-on-Chip Using Computation Slicing. | Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra |
| 2004 | VLSID | Towards The Complete Elimination of Gate/Switch Level Simulations. | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
| 2003 | WISA | Model Checking of Security Protocols with Pre-configuration. | Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra |
| 2002 | ITC | Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. | Jayanta Bhadra, Narayanan Krishnamurthy |
| 2002 | VTS | Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
| 2002 | VTS | Program Slicing for Hierarchical Test Generation. | Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra |
| 2001 | DATE | Full chip false timing path identification: applications to the PowerPCTM microprocessors. | Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham |
| 2000 | VLSID | Automatic Validation Test Generation Using Extracted Control Models. | Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham |
| 1999 | ICCD | Improving Witness Search Using Orders on States. | Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham |