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Jean-Didier Legat

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

35

Venues

16

Active years

1992–2020

Best venue rank

A*

Where they publish

Papers

35 indexed papers, newest first.

YearVenueTitleAuthors
2020ISCASA 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas.Charlotte Frenkel, Jean-Didier Legat, David Bol
2019ISCASA 65-nm 738k-Synapse/mmCharlotte Frenkel, Jean-Didier Legat, David Bol
2017ISCASA fully-synthesized 20-gate digital spike-based synapse with embedded online learning.Charlotte Frenkel, Giacomo Indiveri, Jean-Didier Legat, David Bol
2014ISCASBellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes.Franois Botman, Julien De Vos, Sebastien Bernard, Franois Stas, Jean-Didier Legat, David Bol
2011ISCASCombining sdm-based circuit switching with packet switching in a NoC for real-time applications.Angelo Kuti Lusala, Jean-Didier Legat
2010ISCASRobustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.David Bol, Cdric Hocquet, Denis Flandre, Jean-Didier Legat
2010ISCASCombining circuit and packet switching with bus architecture in a NoC for real-time applications.Angelo Kuti Lusala, Jean-Didier Legat
2009ISLPEDTechnology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.David Bol, Denis Flandre, Jean-Didier Legat
2009ISLPEDNanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat
2009IWCMCFlexible embedded system for sensor integration and custom data processing in an automotive application.Lotfi Guedria, Damien Hubaux, Mathieu Ocaa, Jean-Didier Legat
2008ICCDAnalysis and minimization of practical energy in 45nm subthreshold logic circuits.David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2007DATEInteractive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics.Philippe Manet, Daniel Maufroid, Leonardo Tosi, Marco Di Ciano, Olivier Mulertt, Yves Gabriel, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba
2007DATEEnabling certification for dynamic partial reconfiguration using a minimal flow.Bertrand Rousseau, Philippe Manet, D. Galerin, D. Merkenbreack, Jean-Didier Legat, F. Dedeken, Yves Gabriel
2007FPLNoC Implementation in FPGA Using Torus Topology.Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat
2006DATEApplication-specific reconfigurable XOR-indexing to eliminate cache conflict misses.Hans Vandierendonck, Philippe Manet, Jean-Didier Legat
2004FSEICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware.Franois-Xavier Standaert, Gilles Piret, Gal Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
2003CHESEfficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs.Franois-Xavier Standaert, Gal Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
2003FPGADesign strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES.Gal Rouvroy, Franois-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
2003FPGAA methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL.Franois-Xavier Standaert, Gal Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
2003FPLDesign Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES.Gal Rouvroy, Franois-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
2002CHESA Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results.Franois-Xavier Standaert, Gal Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
2002FPLAn FPGA Implementation of the Linear Cryptanalysis.Franois Koeune, Gal Rouvroy, Franois-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat
2002FPLA Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation.Jean-Jacques Quisquater, Franois-Xavier Standaert, Gal Rouvroy, Jean-Pierre David, Jean-Didier Legat
1999EuroParA Graph-Oriented Task Manager for Small Multiprocessor Systems.Xavier Verians, Jean-Didier Legat, Jean-Jacques Quisquater, Benot Macq
1998ICIPEfficient Parallelisation of an MPEG-2 Codec on a TMS320C80 Video Processor.Olivier Cantineau, Jean-Didier Legat
1998RSPA Data-Flow Oriented Co-Design for Reconfigurable Systems.Jean-Pierre David, Jean-Didier Legat
1996ICIPResolution reduction by growth of zones for visual prosthesis.Tanguy Gilmont, Xavier Verians, Jean-Didier Legat, Claude Veraart
1995ESANNSuboptimal Bayesian classification by vector quantization with small clusters.Jean-Luc Voz, Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1995IWANNAn Associative Processor Dedicated to Classification by Neural Methods.Philippe Thissen, Michel Verleysen, Jean-Didier Legat
1995IWANNA VLSI System for Neural Bayesian and LVQ Classification.Philippe Thissen, Michel Verleysen, Jean-Didier Legat, Jordi Madrenas, Jordi Domnguez
1995IWANNA Practical View of Suboptimal Bayesian Classification with Radial Gaussian Kernels.Jean-Luc Voz, Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1993ESANNOptimal decision surfaces in LVQ1 classiffication of patterns.Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1993IWANNLinear Vector Classification: An Improvement on LVQ Algorithms to Create Classes of Patterns.Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1993VCIPSystolic implementation of a bidimensional lattice filter bank for multiresolution image coding.Pierre Desneux, Jean-Didier Legat, Benot Macq, Jean-Yves Merts
1992ICPRA real-time VLSI-based architecture for multi-motion estimation.Jean-Didier Legat, J. P. Cornil, Damien Macq, Michel Verleysen