| 2016 | PDP | SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC. | Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid |
| 2015 | FCCM | Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System. | Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser |
| 2015 | FPGA | A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only). | Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache |
| 2015 | WCAE | Adopting new learning strategies for computer architecture in higher education: case study: building the S3 microprocessor in 24 hours. | Jean-Luc Dekeyser, A. Shadi Aljendi |
| 2014 | FPGA | Redefining the role of FPGAs in the next generation avionic systems (abstract only). | Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache |
| 2013 | DSD | Master-Slave Control Structure for Massively Parallel System on Chip. | Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser |
| 2012 | DSD | Semi-distributed Control for FPGA-based Reconfigurable Systems. | Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser |
| 2012 | RSP | Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. | Gilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser |
| 2011 | ICCD | Hybrid system level power consumption estimation for FPGA-based MPSoC. | Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smal Niar, Eric Senn, Jean-Luc Dekeyser |
| 2011 | RSP | A model-driven based framework for rapid parallel SoC FPGA prototyping. | Mouna Baklouti, Manel Ammar, Philippe Marquet, Mohamed Abid, Jean-Luc Dekeyser |
| 2010 | DSD | Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. | Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser |
| 2010 | FPL | IP Based Configurable SIMD Massively Parallel SoC. | Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser |
| 2010 | MODELS | Traceability for Mutation Analysis in Model Transformation. | Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser |
| 2009 | AICCSA | Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA. | Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser |
| 2009 | DSD | Model-Driven Design of Embedded Multimedia Applications on SoCs. | Adolf Samir Abdallah, Abdoulaye Gamati, Jean-Luc Dekeyser |
| 2009 | DSD | A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. | Hajer Chtioui, Rabie Ben Atitallah, Smal Niar, Jean-Luc Dekeyser, Mohamed Abid |
| 2009 | ICSoft | Traceability Mechanism for Error Localization in Model Transformation. | Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser |
| 2009 | ICSoft | Using Trace to Situate Errors in Model Transformations. | Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser |
| 2008 | FDL | MARTE-based Design of a Multimedia Application and Formal Analysis. | Adolf Samir Abdallah, Abdoulaye Gamati, Jean-Luc Dekeyser |
| 2008 | ISPDC | Modeling and Formal Validation of High-Performance Embedded Systems. | Abdoulaye Gamati, ric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser |
| 2008 | PDP | A Graphical Framework for High Performance Computing Using An MDE Approach. | Julien Taillard, Frdric Guyomarc'h, Jean-Luc Dekeyser |
| 2007 | FDL | MARTE: UML-based Hardware Design from Modelling to Simulation. | Safouan Taha, Ansgar Radermacher, Sbastien Grard, Jean-Luc Dekeyser |
| 2007 | FDL | Model Transformations from a Data Parallel Formalism towards Synchronous Languages. | Huafeng Yu, Abdoulaye Gamati, ric Rutten, Jean-Luc Dekeyser |
| 2007 | FPL | A Design Flow to Map Parallel Applications onto FPGAs. | Sbastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser |
| 2007 | RTCSA | An MPSoC Performance Estimation Framework Using Transaction Level Modeling. | Rabie Ben Atitallah, Smal Niar, Samy Meftali, Jean-Luc Dekeyser |
| 2006 | DSD | FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. | Sbastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser |
| 2006 | FDL | UML2 Profile for Modeling Controlled Data Parallel Applications. | Ouassila Labbani, ric Rutten, Jean-Luc Dekeyser, Pierre Boulet |
| 2006 | VTC | Safe Design Methodology for an Intelligent Cruise Control System with GPS. | Ouassila Labbani, ric Rutten, Jean-Luc Dekeyser |
| 2005 | FDL | Traceability and Interoperability in Models Transformations. | Lossan Bonde, Pierre Boulet, Jean-Luc Dekeyser |
| 2005 | FDL | Embed Scripting inside SystemC. | J. Vennin, S. Penain, Luc Charest, Samy Meftali, Jean-Luc Dekeyser |
| 2005 | PPAM | Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. | ric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser |
| 2004 | FDL | Metamodels and MDA Transformations for Embedded Systems. | Lossan Bonde, Cdric Dumoulin, Jean-Luc Dekeyser |
| 2004 | FDL | Regular Hardware Architecture Modeling with UML2. | Arnaud Cuccuru, Pierre Boulet, Jean-Luc Dekeyser |
| 2004 | FDL | MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. | M. Samyn, Samy Meftali, Jean-Luc Dekeyser |
| 2004 | FDL | An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). | E. Turbatu, Samy Meftali, Smal Niar, Jean-Luc Dekeyser |
| 2004 | PDP | The Effect of the Degree of Multistage Interconnection Networks on their Performance: The Case of Delta and Over-Sized Delta Networks. | Ahmad Chadi Aljundi, Jean-Luc Dekeyser |
| 2003 | FDL | MDA for SoC Design, Intensive Signal Processing Experiment. | Pierre Boulet, Jean-Luc Dekeyser, Cdric Dumoulin, Philippe Marquet |
| 2003 | FDL | Interoperability between Design and Simulation Tools using Model Transformation Techniques. | Cdric Dumoulin, Jean-Luc Dekeyser, Boris Kokoszko, S. Pulon, G. Cristau |
| 2001 | PACT | Compilation Principle of a Specification Language Dedicated to Signal Processing. | Julien Soula, Philippe Marquet, Alain Demeure, Jean-Luc Dekeyser |
| 2001 | PDP | Visual Data-Parallel Programming for Signal Processing Applications. | Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, Alain Demeure |
| 1996 | EuroPar | Dynamic Redistribution on Heterogeneous Parallel Computers. | Dominique Sueur, Jean-Luc Dekeyser |
| 1996 | ICIP | Mixed synchronous-asynchronous approach for real-time image processing: a MPEG-like coder. | David Galinec, Jean-Luc Dekeyser, Philippe Marquet |
| 1993 | HCI | HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages. | Akram-Djellal Benalia, Jean-Luc Dekeyser, Philippe Marquet |
| 1992 | ISCA | Performance improvement for vector pipeline multiprocessor systems using a disordered execution model. | M. Tahar Kechadi, Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux |