| 2014 | ICASSP | 3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system. | Hsien-Ching Hsieh, Yi-Fa Sun, Jen-Chieh Yeh, Po-Han Huang |
| 2013 | ASPDAC | Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. | Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu |
| 2012 | HPCC | Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement. | Yi-Fa Sun, Chun-Nan Liu, Tse-Min Chen, Hsien-Ching Hsieh, Jen-Chieh Yeh, Yung-Chang Chang |
| 2011 | DAC | PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. | Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh |
| 2011 | HPCC | Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology. | Jen-Chieh Yeh, Kung-Ming Ji, Shing-Wu Tung, Shau-Yin Tseng |
| 2010 | ASPDAC | PAC duo system power estimation at ESL. | Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang |
| 2010 | DATE | An accurate system architecture refinement methodology with mixed abstraction-level virtual platform. | Zhe-Mao Hsu, Jen-Chieh Yeh, I-Yao Chuang |
| 2007 | VTS | SDRAM Delay Fault Modeling and Performance Testing. | Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu |
| 2006 | DAC | A network security processor design based on an integrated SOC design and test platform. | Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang |
| 2006 | ITC | An Enhanced EDAC Methodology for Low Power PSRAM. | Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin |
| 2005 | VTS | Flash Memory Built-In Self-Diagnosis with Test Mode Control. | Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin |
| 2003 | ITC | A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. | Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow |
| 2002 | IOLTS | A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |
| 2002 | ITC | Diagonal Test and Diagnostic Schemes for Flash Memorie. | Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu |
| 2002 | VTS | RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. | Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu |