| 2024 | IJCNN | SARA: Semantic-assisted Reinforced Active Learning for Entity Alignment. | Ching-Hsuan Liu, Chih-Ming Chen, Jing-Kai Lou, Ming-Feng Tsai, Jiun-Lang Huang, Chuan-Ju Wang |
| 2020 | ETS | Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model. | Ching-Yuan Chen, Ching-Hong Cheng, Jiun-Lang Huang, Krishnendu Chakrabarty |
| 2020 | ICCAD | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. | Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen |
| 2019 | DDECS | Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. | Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang |
| 2013 | ETS | A mutual characterization based SAR ADC self-testing technique. | H.-J. Lin, Xuan-Lun Huang, Jiun-Lang Huang |
| 2013 | ICCAD | An IDDQ-based source driver IC design-for-test technique. | S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang |
| 2013 | ITC | A circular pipeline processing based deterministic parallel test pattern generator. | Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang |
| 2013 | VLSID | On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. | Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang |
| 2012 | VTS | A SAR ADC missing-decision level detection and removal technique. | Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai |
| 2011 | ASPDAC | A self-testing and calibration method for embedded successive approximation register ADC. | Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu |
| 2011 | ETS | A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. | Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai |
| 2011 | ITC | Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. | Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen |
| 2010 | ASPDAC | Improved weight assignment for logic switching activity during at-speed test pattern generation. | Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng |
| 2010 | DAC | An error tolerance scheme for 3D CMOS imagers. | Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu |
| 2010 | DATE | A robust ADC code hit counting technique. | Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang |
| 2010 | ICCAD | A scalable quantitative measure of IR-drop effects for scan pattern generation. | Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli |
| 2010 | VTS | An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. | Xuan-Lun Huang, Jiun-Lang Huang |
| 2010 | VTS | CSER: BISER-based concurrent soft-error resilience. | Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li |
| 2009 | ASPDAC | Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. | Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang |
| 2008 | ITC | Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing. | Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase |
| 2008 | VTS | A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. | Chen-Wei Lin, Jiun-Lang Huang |
| 2006 | ASPDAC | A routability constrained scan chain ordering technique for test power reduction. | Xuan-Lun Huang, Jiun-Lang Huang |
| 2004 | ICCD | An Infrastructure IP for On-Chip Clock Jitter Measurement. | Jui-Jer Huang, Jiun-Lang Huang |
| 2001 | VTS | An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. | Jiun-Lang Huang, Kwang-Ting Cheng |
| 2000 | ASPDAC | A sigma-delta modulation based BIST scheme for mixed-signal circuits. | Jiun-Lang Huang, Kwang-Ting Cheng |
| 2000 | DATE | A BIST Scheme for On-Chip ADC and DAC Testing. | Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng |
| 2000 | ITC | Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. | Jiun-Lang Huang, Kwang-Ting Cheng |
| 2000 | VTS | Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. | Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng |
| 1999 | VTS | Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. | Jiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng |
| 1997 | ITC | Analog Fault Diagnosis for Unpowered Circuit Boards. | Jiun-Lang Huang, Kwang-Ting Cheng |