Joel S. Emer
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
100
Venues
19
Active years
1984–2026
Best venue rank
A*
Where they publish
Papers
100 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ASPLOS | Insum: Sparse GPU Kernels Simplified and Optimized with Indirect Einsums. | Jaeyeon Won, Willow Ahrens, Saman P. Amarasinghe, Joel S. Emer |
| 2026 | ISCA | Lotus: A Multi-FPGA Task Dataflow Architecture to Accelerate Cycle-Level Simulation. | Fares Elsabbagh, Joel S. Emer, Daniel Snchez |
| 2025 | ASPLOS | Hopps: Leveraging Sparsity to Accelerate Automata Processing. | Xingran Du, Joel S. Emer, Daniel Snchez |
| 2025 | MICRO | Quartz: A Reconfigurable, Distributed-Memory Accelerator for Sparse Applications. | Courtney Golden, Axel Feldmann, Joel S. Emer, Daniel Snchez |
| 2024 | ISCA | Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms. | Qijing Huang, Po-An Tsai, Joel S. Emer, Angshuman Parashar |
| 2024 | ISCA | Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications. | Yifan Yang, Joel S. Emer, Daniel Snchez |
| 2024 | ISPASS | Architecture-Level Modeling of Photonic Deep Neural Network Accelerators. | Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar, Joel S. Emer, Vivienne Sze |
| 2024 | ISPASS | CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool. | Tanner Andrulis, Joel S. Emer, Vivienne Sze |
| 2024 | MICRO | DelayAVF: Calculating Architectural Vulnerability Factors for Delay Faults. | Peter W. Deutsch, Vincent Quentin Ulitzsch, Sudhanva Gurumurthi, Vilas Sridharan, Joel S. Emer, Mengjia Yan |
| 2024 | MICRO | Azul: An Accelerator for Sparse Iterative Solvers Leveraging Distributed On-Chip Memory. | Axel Feldmann, Courtney Golden, Yifan Yang, Joel S. Emer, Daniel Snchez |
| 2024 | MICRO | FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design. | Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher |
| 2023 | ASPLOS | The Sparse Abstract Machine. | Olivia Hsu, Maxwell Strange, Ritvik Sharma, Jaeyeon Won, Kunle Olukotun, Joel S. Emer, Mark A. Horowitz, Fredrik Kjlstad |
| 2023 | ASPLOS | Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. | Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher |
| 2023 | ASPLOS | WACO: Learning Workload-Aware Co-optimization of the Format and Schedule of a Sparse Tensor Program. | Jaeyeon Won, Charith Mendis, Joel S. Emer, Saman P. Amarasinghe |
| 2023 | DCC | Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. | Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer |
| 2023 | HPCA | ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining. | Yifan Yang, Joel S. Emer, Daniel Snchez |
| 2023 | ISCA | RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! | Tanner Andrulis, Joel S. Emer, Vivienne Sze |
| 2023 | ISCA | Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes. | Peter W. Deutsch, Weon Taek Na, Thomas Bourgeat, Joel S. Emer, Mengjia Yan |
| 2023 | ISPASS | LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. | Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2023 | MICRO | Accelerating RTL Simulation with Hardware-Software Co-Design. | Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Snchez |
| 2023 | MICRO | SecureLoop: Design Space Exploration of Secure DNN Accelerators. | Kyungmi Lee, Mengjia Yan, Joel S. Emer, Anantha P. Chandrakasan |
| 2023 | MICRO | TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. | Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer |
| 2023 | MICRO | HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. | Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2023 | MICRO | Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. | Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze |
| 2022 | ASPLOS | DAGguise: mitigating memory timing side channels. | Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel S. Emer, Mengjia Yan |
| 2022 | ISPASS | Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization. | Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel S. Emer, Siddharth Joshi |
| 2022 | MICRO | Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. | Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2021 | ASPLOS | Gamma: leveraging Gustavson's algorithm to accelerate sparse matrix multiplication. | Guowei Zhang, Nithya Attaluri, Joel S. Emer, Daniel Snchez |
| 2021 | ISCA | SpZip: Architectural Support for Effective Data Compression In Irregular Applications. | Yifan Yang, Joel S. Emer, Daniel Snchez |
| 2021 | ISPASS | Architecture-Level Energy Estimation for Heterogeneous Computing Systems. | Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze |
| 2021 | ISPASS | Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. | Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2021 | WCAE | Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future. | Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, Joel S. Emer |
| 2020 | ISPASS | An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. | Yannan Nellie Wu, Vivienne Sze, Joel S. Emer |
| 2020 | MICRO | CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches. | Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan |
| 2019 | ASPLOS | Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. | Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer |
| 2019 | ICCAD | MAGNet: A Modular Accelerator Generator for Neural Networks. | Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany |
| 2019 | ICCAD | Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. | Yannan Nellie Wu, Joel S. Emer, Vivienne Sze |
| 2019 | ISPASS | Timeloop: A Systematic Approach to DNN Accelerator Evaluation. | Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer |
| 2019 | MICRO | ExTensor: An Accelerator for Sparse Tensor Algebra. | Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher |
| 2019 | MICRO | Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. | Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler |
| 2018 | DAC | A modular digital VLSI flow for high-productivity SoC design. | Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer |
| 2018 | MICRO | Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism. | Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel S. Emer, Daniel Snchez |
| 2018 | MICRO | DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors. | Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer |
| 2017 | ACSSC | A method to estimate the energy consumption of deep neural networks. | Tien-Ju Yang, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze |
| 2017 | FPGA | Automatic Construction of Program-Optimized FPGA Memory Networks. | Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer |
| 2017 | ISCA | SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. | Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally |
| 2017 | ISCA | Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism. | Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel S. Emer, Daniel Snchez |
| 2017 | ISCAS | Towards closing the energy gap between HOG and CNN features for embedded vision (Invited paper). | Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze |
| 2017 | ISPASS | SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation. | Siva Kumar Sastry Hari, Timothy Tsai, Mark Stephenson, Stephen W. Keckler, Joel S. Emer |
| 2017 | SC | Understanding error propagation in deep learning neural network (DNN) accelerators and applications. | Guanpeng Li, Siva Kumar Sastry Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel S. Emer, Stephen W. Keckler |
| 2016 | FPGA | LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning. | Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer |
| 2016 | ISCA | Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. | Yu-Hsin Chen, Joel S. Emer, Vivienne Sze |
| 2016 | MICRO | Data-centric execution of speculative parallel programs. | Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Snchez |
| 2015 | FPL | Scavenger: Automating the construction of application-optimized memory hierarchies. | Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer |
| 2015 | HPCA | High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches. | Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer |
| 2015 | MICRO | A scalable architecture for ordered parallelism. | Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Snchez |
| 2015 | MICRO | A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. | Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer |
| 2014 | FCCM | LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories. | Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer |
| 2014 | FPL | The LEAP FPGA operating system. | Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer |
| 2014 | ISPASS | Exploiting spatial architectures for edit distance algorithms. | Jesmin Jahan Tithi, Neal Clayton Crago, Joel S. Emer |
| 2013 | FPL | Optimizing under abstraction: Using prefetching to improve FPGA performance. | Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer |
| 2013 | ISCA | Triggered instructions: a control paradigm for spatially-programmed architectures. | Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer |
| 2012 | ASPLOS | CRUISE: cache replacement and utility-aware scheduling. | Aamer Jaleel, Hashem Hashemi Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr., Joel S. Emer |
| 2012 | FPGA | Leveraging latency-insensitivity to ease multiple FPGA design. | Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer |
| 2012 | ISCA | Scheduling heterogeneous multi-cores through performance impact estimation (PIE). | Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narvez, Joel S. Emer |
| 2011 | FPGA | Leap scratchpads: automatic memory and cache management for reconfigurable logic. | Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer |
| 2011 | HPCA | HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. | Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer |
| 2011 | MICRO | SHiP: signature-based hit predictor for high performance caching. | Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer |
| 2011 | MICRO | PACMan: prefetch-aware cache management for high performance caching. | Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer |
| 2010 | ISCA | High performance cache replacement using re-reference interval prediction (RRIP). | Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer |
| 2010 | MEMOCODE | Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). | Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer |
| 2010 | MICRO | Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies. | Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer |
| 2009 | DAC | Soft connections: addressing the hardware-design modularity problem. | Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer |
| 2009 | HPCA | CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. | Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit Riaz Sheikh, Shrirang M. Yardi |
| 2009 | ISPASS | Accelerating architecture research. | Joel S. Emer |
| 2008 | FPGA | A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer |
| 2008 | ISPASS | Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer |
| 2007 | ISCA | Adaptive insertion policies for high performance caching. | Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer |
| 2007 | ISCA | Late-binding: enabling unordered load-store queues. | Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler |
| 2005 | HPCA | The Soft Error Problem: An Architectural Perspective. | Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt |
| 2005 | ISCA | Computing Architectural Vulnerability Factors for Address-Based Structures. | Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan |
| 2004 | ISCA | Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. | Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt |
| 2004 | PRDC | Cache Scrubbing in Microprocessors: Myth or Necessity? | Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt |
| 2003 | MICRO | A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. | Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin |
| 2002 | ASPLOS | A comparative study of arbitration algorithms for the Alpha 21364 pipelined router. | Shubhendu S. Mukherjee, Federico Silla, Peter J. Bannon, Joel S. Emer, Steven Lang, David Webb |
| 2002 | HPCA | Loose Loops Sink Chips. | Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer |
| 2002 | ISCA | Tarantula: A Vector Extension to the Alpha Architecture. | Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, Andr Seznec |
| 2000 | HPCA | Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. | Harish Patil, Joel S. Emer |
| 1999 | ICS | Reducing cache misses using hardware and software page placement. | Timothy Sherwood, Brad Calder, Joel S. Emer |
| 1999 | MICRO | The Use of Multithreading for Exception Handling. | Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi |
| 1998 | ISCA | Memory Dependence Prediction Using Store Sets. | George Z. Chrysos, Joel S. Emer |
| 1998 | ISCA | Retrospective: Characterization of Processor Performance in the VAX-11/780. | Joel S. Emer, Douglas W. Clark |
| 1998 | ISCA | A Characterization of Processor Performance in the VAX-11/780. | Joel S. Emer, Douglas W. Clark |
| 1997 | ISCA | A Language for Describing Predictors and Its Application to Automatic Synthesis. | Joel S. Emer, Nicholas C. Gloy |
| 1996 | HPCA | Predictive Sequential Associative Cache. | Brad Calder, Dirk Grunwald, Joel S. Emer |
| 1996 | ISCA | Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. | Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm |
| 1995 | ISCA | Instruction Fetching: Coping with Code Bloat. | Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer |
| 1995 | MICRO | A system level perspective on branch architecture performance. | Brad Calder, Dirk Grunwald, Joel S. Emer |
| 1988 | ICDCS | Performance Considerations for Distributed Services: A Case Study: Mass Storage. | Joel S. Emer, K. K. Ramakrishnan |
| 1984 | ISCA | A Characterization of Processor Performance in the VAX-11/780. | Joel S. Emer, Douglas W. Clark |