| 2020 | FPL | Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. | Nuno Paulino, Joo Canas Ferreira, Joo Bispo, Joo M. P. Cardoso |
| 2018 | DSD | Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing. | Helder H. Avelar, Joo Canas Ferreira |
| 2018 | ISCAS | Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator. | Mrio Lopes Ferreira, Joo Canas Ferreira |
| 2015 | DATE | Transparent acceleration of program execution using reconfigurable hardware. | Nuno Miguel Cardanha Paulino, Joo Canas Ferreira, Joo Bispo, Joo M. P. Cardoso |
| 2015 | DSD | An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem. | Pedro Vieira dos Santos, Jos Carlos Alves, Joo Canas Ferreira |
| 2015 | EUC | Reconfigurable NC-OFDM Processor for 5G Communications. | Mrio Lopes Ferreira, Joo Canas Ferreira |
| 2014 | DSD | A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks. | Fardin Derogarian, Joo Canas Ferreira, Vtor M. Grade Tavares |
| 2014 | ISPA | Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. | Nuno Miguel Cardanha Paulino, Joo Canas Ferreira, Joo Manuel Paiva Cardoso |
| 2013 | DSD | Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques. | Filipe Sousa, Francis Anghinolfi, Joo Canas Ferreira |
| 2013 | FPL | A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio. | Pedro Vieira dos Santos, Jos Carlos Alves, Joo Canas Ferreira |
| 2012 | DSD | Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks. | Fardin Derogarian, Joo Canas Ferreira, Vtor M. Grade Tavares |
| 2010 | DSD | Creation of Partial FPGA Configurations at Run-Time. | Miguel Lino Silva, Joo Canas Ferreira |
| 2010 | FPL | Erlang Inspired Hardware. | Paulo Ferreira, Joo Canas Ferreira, Jos Carlos Alves |
| 2008 | FPL | Generation of partial FPGA configurations at run-time. | Miguel Lino Silva, Joo Canas Ferreira |
| 2005 | DSD | Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. | Miguel Lino Silva, Joo Canas Ferreira |
| 2004 | FPL | A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. | Joo Canas Ferreira, Jos Silva Matos |
| 1999 | FCCM | FAFNER-Accelerating Nesting Problems with FPGAs. | Jos Carlos Alves, Joo Canas Ferreira, C. Albuquerque, Jos Fernando Oliveira, Jos Soeiro Ferreira, Jos Silva Matos |
| 1998 | FCCM | A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. | Joo Canas Ferreira, Jos Silva Matos |
| 1994 | ISCAS | An Approach to Testability Improvement of Mixed-Signal Boards. | Jos Silva Matos, Joo Canas Ferreira, Ana C. Leo, Jos Machado da Silva |
| 1994 | VTS | Architecture of test support ICs for mixed-signal testing. | Jos Silva Matos, Joo Canas Ferreira, Ana C. Leo, Jos Machado da Silva |
| 1993 | ITC | Control and Observation of Analog Nodes in Mixed-Signal Boards. | Jos Silva Matos, Ana C. Leo, Joo Canas Ferreira |