| 2026 | VLSID | All-Digital Ring Oscillator with Feature of Auto Frequency Tuning Using Serial Data. | Himanshu N. Patel, Chiragkumar Patel, Joycee Mekie, Hari Shankar Gupta, B. Saravana Kumar |
| 2025 | ISCAS | VeriBench: Benchmarking Large Language Models for Verilog Code Generation and Design Synthesis. | Mihir Agarwal, Zaqi Momin, Kailash Prasad, Joycee Mekie |
| 2025 | ISCAS | DTQ-16T: Double Node Upset Tolerant Quadruple SRAM for Space Applications. | Pramod Kumar Bharti, Govind Prasad, Mukku Pavan Kumar, Joycee Mekie |
| 2025 | VLSID | HyCMAx: Power-Efficient Hybrid CMOS-Memristor Based Approximate Dividers for Error-Resilient Applications. | Monika Pokharia, Het Trivedi, Siddharth Doshi, Ravi S. Hegde, Joycee Mekie |
| 2025 | VLSID | OwlsEye: Real-Time Low-Light Video Instance Segmentation on Edge and Exploration of Fixed-Posit Quantization. | Gaurav Shah, Abhinav Goud, Zaqi Momin, Joycee Mekie |
| 2024 | ASPDAC | CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs. | Tom Glint, Manu Awasthi, Joycee Mekie |
| 2024 | ASPDAC | Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data. | Tom Glint, Manu Awasthi, Joycee Mekie |
| 2024 | DATE | DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators. | Tom Glint, Mithil Pechimuthu, Joycee Mekie |
| 2024 | VLSID | FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing. | Yathin Kumar Attuluri, Ruchit Chudasama, Kailash Prasad, Joycee Mekie |
| 2024 | VLSID | FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC. | Saketh Gajawada, Aryan Gupta, Kailash Prasad, Joycee Mekie |
| 2024 | VLSID | COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators. | Vrajesh Patel, Neel Shah, Aravind Krishna, Tom Glint, Abdul Ronak, Joycee Mekie |
| 2024 | VLSID | Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications. | Monika Pokharia, Kailash Prasad, Ravi S. Hegde, Joycee Mekie |
| 2024 | VLSID | SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space. | Kailash Prasad, Neel Shah, Jinay Dagli, Joycee Mekie |
| 2023 | ASPDAC | Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers. | Tom Glint, Kailash Prasad, Jinay Dagli, Krishil Gandhi, Aryan Gupta, Vrajesh Patel, Neel Shah, Joycee Mekie |
| 2023 | DAC | PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs. | Sai Shubham, Shubham Pandit, Kailash Prasad, Joycee Mekie |
| 2023 | DATE | REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet. | Tom Glint, Manu Awasthi, Joycee Mekie |
| 2023 | DATE | Analysis of Quantization Across DNN Accelerator Architecture Paradigms. | Tom Glint, Chandan Kumar Jha, Manu Awasthi, Joycee Mekie |
| 2023 | DATE | PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM. | Kailash Prasad, Aditya Biswas, Arpita Kabra, Joycee Mekie |
| 2023 | DATE | Process Variation Resilient Current-Domain Analog In Memory Computing. | Kailash Prasad, Sai Shubham, Aditya Biswas, Joycee Mekie |
| 2023 | ISPASS | Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA. | Tom Glint, Aryan Gupta, Daniel Giftson, Gaurav Shah, Vrajesh Patel, Ruchit Chudasama, Sukanya More, Joycee Mekie |
| 2023 | ISPASS | Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators. | Tom Glint, Chandan Kumar Jha, Manu Awasthi, Joycee Mekie |
| 2023 | VLSID | Fast and Robust Sense Amplifier for Digital In Memory Computing. | Kailash Prasad, Ayush Srivastava, Nistha Baruah, Joycee Mekie |
| 2022 | ICCD | RHSCC-16T: Radiation Hardened Sextuple Cross Coupled Robust SRAM Design for Radiation Prone Environments. | Pramod Kumar Bharti, Joycee Mekie |
| 2022 | ISCAS | Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads. | Pramod Kumar Bharti, Saurabh Jain, Kamlesh R. Pillai, Sagar Varma Sayyaparaju, Gurpreet S. Kalsi, Joycee Mekie, Sreenivas Subramoney |
| 2022 | ISCAS | An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs. | Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie |
| 2022 | VLSID | Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks. | Neelam Surana, Pramod Kumar Bharti, Bachu Varun Tej, Joycee Mekie |
| 2021 | ISCAS | FPCAM: Floating Point Configurable Approximate Multiplier for Error Resilient Applications. | Chandan Kumar Jha, Sumit Walia, Gagan Kanojia, Joycee Mekie |
| 2020 | DATE | Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing. | Neelam Surana, Mili Lavania, Abhishek Barma, Joycee Mekie |
| 2020 | ICCD | ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator. | Tom Glint, Jitesh Sah, Manu Awasthi, Joycee Mekie |
| 2020 | ISCAS | FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers. | Chandan Kumar Jha, Kailash Prasad, Vibhor Kumar Srivastava, Joycee Mekie |
| 2020 | ISCAS | SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors. | Chandan Kumar Jha, Kailash Prasad, Arun Singh Tomar, Joycee Mekie |
| 2020 | ISCAS | A Low-Voltage Split Memory Architecture for Binary Neural Networks. | Joydeep Kumar Devnath, Neelam Surana, Joycee Mekie |
| 2020 | VLSID | A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks. | Joydeep Kumar Devnath, Neelam Surana, Joycee Mekie |
| 2019 | DAC | SEDA - Single Exact Dual Approximate Adders for Approximate Processors. | Chandan Kumar Jha, Joycee Mekie |
| 2019 | DSD | Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs. | Chandan Kumar Jha, Joycee Mekie |
| 2019 | VLSID | Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications. | Pramod Kumar Bharti, Neelam Surana, Joycee Mekie |
| 2019 | VLSID | Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop. | Shubhanshu Gupta, Joycee Mekie |
| 2018 | VLSID | Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique. | Sai Aparna Aketi, Joycee Mekie, Hemal Shah |
| 2018 | VLSID | Impact of Variations on Synchronizer Performance: An Experimental Study. | Joycee Mekie, Prashansa Mukim, Kimaya Kale |
| 2014 | VLSID | Tutorial T7B: Network on Chips - The Journey Overview. | Joycee Mekie, Sneha N. Ved |
| 2004 | VLSID | Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework. | Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma |