Jrg E. Vollrath
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
1997–2015
Best venue rank
C
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | EDUCON | An open access minimum automatic task generation live feedback system for electrical engineering. | Jrg E. Vollrath |
| 2014 | EDUCON | Interactive tools for teaching electrical engineering. | Jrg E. Vollrath |
| 2013 | EDUCON | Using models, simulation and measurements for teaching circuit design. | Jrg E. Vollrath |
| 2006 | ITC | DRAM-Specific Space of Memory Tests. | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jrg E. Vollrath |
| 2001 | ITC | Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. | Jrg E. Vollrath, Randall Rooney |
| 2000 | ETS | Compressed bit fail maps for memory fail pattern classification. | Jrg E. Vollrath, Ulf Lederer, Thomas Hladschik |
| 1997 | ITC | Cell Signal Measurement for High-Density DRAMs. | Jrg E. Vollrath |