| 2026 | IOLTS | Impact of Locations of Circuit Components on Multiple Cell Upset Mitigation in a 22 nm Bulk Process. | Shuhei Mandai, Ryuichi Nakajima, Arata Matsumoto, Yusaku Nakaoka, Hikaru Nakamoto, Sotaro Taniguchi, Shinobu Onoda, Jun Furuta, Kazutoshi Kobayashi |
| 2026 | ISCAS | Implementation and Evaluation of a Cryogenic DSP in 22-nm with Floating-Point Arithmetic for Estimating Qubit States. | Yuki Koyama, Takashi Imagawa, Ryo Kishida, Takefumi Miyoshi, Kazutoshi Kobayashi |
| 2025 | ASPDAC | Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. | Dondee Navarro, Shin Taniguchi, Chika Tanaka, Kazutoshi Kobayashi, Takashi Sato, Michihiro Shintani |
| 2025 | IOLTS | Comparative Analysis of TID Effects in a 65 nm FD-SOI Process Under Gamma-Ray and Alpha-Ray Irradiation. | Hikaru Nakamoto, Taiki Ozawa, Ryuichi Nakajima, Haruto Sugisaki, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi |
| 2025 | ISCAS | A 22-nm Surface Code Decoder Using Greedy Algorithm. | Junichiro Kadomoto, Ren Aoyama, Kazutoshi Kobayashi |
| 2024 | QCE | A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment. | Takashi Imagawa, Ryo Kishida, Yuki Koyama, Kazutoshi Kobayashi, Takefumi Miyoshi |
| 2023 | IOLTS | Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation. | Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard |
| 2022 | IOLTS | Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process. | Ryuichi Nakajima, Kazuya Ioki, Jun Furuta, Kazutoshi Kobayashi |
| 2019 | IOLTS | Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process. | Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi |
| 2019 | IOLTS | Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement. | Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi |
| 2019 | IOLTS | Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process. | Takashi Yoshida, Kazutoshi Kobayashi, Jun Furuta |
| 2015 | ASPDAC | Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. | Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera |
| 2011 | ASPDAC | A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. | Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2010 | PRDC | A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. | Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi |
| 2008 | ASPDAC | Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. | Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2008 | FPGA | Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. | Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2008 | FPL | A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. | Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera |
| 2008 | FPL | Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. | Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2007 | ASPDAC | A 90nm 816 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. | Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2006 | ASPDAC | Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. | Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2006 | FPL | A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. | Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera |
| 2005 | ASPDAC | A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. | Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera |
| 2004 | ASPDAC | An SoC architecture and its design methodology using unifunctional heterogeneous processor array. | Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2004 | ISCAS | RTL/ISS co-modeling methodology for embedded processor using SystemC. | Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2001 | ASPDAC | A vector-pipeline DSP for low-rate videophones. | Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera |
| 2001 | ISCAS | ST: PERL package for simulation and test environment. | Kazutoshi Kobayashi, Hidetoshi Onodera |
| 1998 | ICASSP | Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. | Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru |
| 1997 | ASPDAC | A functional memory type parallel processor for vector quantization. | Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru |