| 2025 | DATE | A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process. | Prashanth Mohan, Siddharth Das, Oguz Atli, Josh Joffrion, Ken Mai |
| 2023 | ISCAS | MANIC: A $19\mu\mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS. | Graham Gobieski, Oguz Atli, Cagri Erbagci, Ken Mai, Nathan Beckmann, Brandon Lucia |
| 2022 | IROS | Towards Specialized Hardware for Learning-based Visual Odometry on the Edge. | Siyuan Chen, Ken Mai |
| 2021 | DATE | Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. | Prashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai |
| 2021 | FPGA | Top-down Physical Design of Soft Embedded FPGA Fabrics. | Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai |
| 2020 | FPGA | A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow. | Prashanth Mohan, Oguz Atli, Onur O. Kibar, Ken Mai |
| 2020 | ICCD | ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS. | Prashanth Mohan, Wen Wang, Bernhard Jungk, Ruben Niederhagen, Jakub Szefer, Ken Mai |
| 2017 | HPCA | Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques. | Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch |
| 2016 | HOTI | Scalable High-Radix Modular Crossbar Switches. | Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai |
| 2015 | HPCA | Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. | Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Onur Mutlu |
| 2015 | ICCAD | Statistical Learning in Chip (SLIC). | Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas |
| 2015 | ISLPED | High-efficiency crossbar switches using capacitively coupled signaling. | Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai |
| 2015 | ISPASS | DELPHI: a framework for RTL-based architecture design evaluation using DSENT models. | Michael Papamichael, Cagla Cakir, Chen Sun, Chia-Hsin Owen Chen, James C. Hoe, Ken Mai, Li-Shiuan Peh, Vladimir Stojanovic |
| 2014 | DATE | An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. | Mudit Bhargava, Ken Mai |
| 2014 | SIGMETRICS | Neighbor-cell assisted error correction for MLC NAND flash memories. | Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman S. Unsal, Adrin Cristal, Ken Mai |
| 2013 | CHES | A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. | Mudit Bhargava, Ken Mai |
| 2013 | DATE | Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. | Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai |
| 2013 | ICCD | Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. | Yu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai |
| 2013 | ITC | SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. | Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai |
| 2013 | PRDC | Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. | Jangwoo Kim, Hyunggyun Yang, Mark P. McCartney, Mudit Bhargava, Ken Mai, Babak Falsafi |
| 2012 | DATE | Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. | Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai |
| 2012 | FPGA | Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. | Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai |
| 2012 | ICCD | Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. | Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrin Cristal, Osman S. nsal, Ken Mai |
| 2011 | FCCM | FPGA-Based Solid-State Drive Prototyping Platform. | Yu Cai, Erich F. Haratsch, Mark P. McCartney, Ken Mai |
| 2011 | FPGA | FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). | Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai |
| 2011 | FPGA | CoRAM: an in-fabric memory architecture for FPGA-based computing. | Eric S. Chung, James C. Hoe, Ken Mai |
| 2010 | DAC | Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. | Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun |
| 2010 | MICRO | Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? | Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai |
| 2009 | ICCD | A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. | Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun |
| 2008 | FPGA | A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. | Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai |
| 2007 | MICRO | Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. | Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe |
| 2000 | ISCA | Smart Memories: a modular reconfigurable architecture. | Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz |
| 1999 | ICCAD | Interconnect scaling implications for CAD. | Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz |