| 2025 | FPGA | TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees. | Alireza Khataei, Kia Bazargan |
| 2024 | FPGA | CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond. | Alireza Khataei, Kia Bazargan |
| 2023 | FCCM | Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures. | Alireza Khataei, Gaurav Singh, Kia Bazargan |
| 2023 | FPGA | Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing. | Alireza Khataei, Gaurav Singh, Kia Bazargan |
| 2023 | ICCAD | Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary Computing. | Alireza Khataei, Kia Bazargan |
| 2020 | FCCM | Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications. | S. Rasoul Faraji, Pierre Abillama, Kia Bazargan |
| 2020 | ICCAD | Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs. | S. Rasoul Faraji, Kia Bazargan |
| 2020 | ISCAS | HBUCNNA: Hybrid Binary-Unary Convolutional Neural Network Accelerator. | S. Rasoul Faraji, Pierre Abillama, Gaurav Singh, Kia Bazargan |
| 2020 | ISCAS | Energy-Efficient Pulse-Based Convolution for Near-Sensor Processing. | M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja |
| 2019 | ASPDAC | Hybrid binary-unary hardware accelerator. | S. Rasoul Faraji, Kia Bazargan |
| 2019 | DATE | Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing. | S. Rasoul Faraji, M. Hassan Najafi, Bingzhe Li, David J. Lilja, Kia Bazargan |
| 2019 | ICCD | HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGA. | Sayed Abdolrasouol Faraji, Gaurav Singh, Kia Bazargan |
| 2018 | ASPDAC | Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks. | Zhiheng Wang, Soheil Mohajer, Kia Bazargan |
| 2018 | FPGA | Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data. | Soheil Mohajer, Zhiheng Wang, Kia Bazargan |
| 2017 | ICCD | Power and Area Efficient Sorting Networks Using Unary Processing. | M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan |
| 2016 | ASPDAC | Polysynchronous stochastic circuits. | M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan |
| 2016 | FPGA | t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only). | Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan |
| 2015 | DAC | Randomness meets feedback: stochastic implementation of logistic map dynamical system. | Zhiheng Wang, Naman Saraf, Kia Bazargan, Arnd Scheel |
| 2015 | DATE | Axilog: language support for approximate hardware design. | Amir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan |
| 2014 | DATE | IIR filters using stochastic arithmetic. | Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel |
| 2014 | FPGA | Binary stochastic implementation of digital logic. | Yanzi Zhu, Peiran Suo, Kia Bazargan |
| 2013 | ICCAD | Sequential logic to transform probabilities. | Naman Saraf, Kia Bazargan |
| 2013 | ICCD | Stochastic functions using sequential logic. | Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel |
| 2012 | ASPDAC | The synthesis of linear Finite State Machine-based Stochastic Computational Elements. | Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja |
| 2012 | ICCAD | The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic. | Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel |
| 2012 | ICCAD | An efficient implementation of numerical integration using logical computation on stochastic bit streams. | Weikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, Marc D. Riedel |
| 2011 | FPGA | FPGA placement by graph isomorphism (abstract only). | Hossein Omidian Savarbaghi, Kia Bazargan |
| 2010 | ASPDAC | A fast SPFD-based rewiring technique. | Pongstorn Maidee, Kia Bazargan |
| 2009 | DATE | Using randomization to cope with circuit uncertainty. | Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan |
| 2009 | ICCAD | The synthesis of combinational logic to generate probabilities. | Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja |
| 2008 | FPL | FPGA family composition and effects of specialized blocks. | Pongstorn Maidee, Nagib Hakim, Kia Bazargan |
| 2008 | ICCAD | Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. | Hushrav Mogal, Kia Bazargan |
| 2007 | DATE | Microarchitecture floorplanning for sub-threshold leakage reduction. | Hushrav Mogal, Kia Bazargan |
| 2007 | FPGA | Variation-aware routing for FPGAs. | Satish Sivaswamy, Kia Bazargan |
| 2007 | FPL | A generalized and unified SPFD-based rewiring technique. | Pongstorn Maidee, Kia Bazargan |
| 2007 | FPL | Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. | Satish Sivaswamy, Kia Bazargan |
| 2007 | ICCAD | Clustering based pruning for statistical criticality computation under process variations. | Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan |
| 2006 | FPL | Defect-Tolerant FPGA Architecture Exploration. | Pongstorn Maidee, Kia Bazargan |
| 2005 | ASPDAC | Three-dimensional place and route for FPGAs. | Cristinel Ababei, Hushrav Mogal, Kia Bazargan |
| 2005 | FPGA | 3D FPGAs: placement, routing, and architecture evaluation (abstract only). | Cristinel Ababei, Hushrav Mogal, Kia Bazargan |
| 2005 | FPGA | HARP: hard-wired routing pattern FPGAs. | Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh |
| 2004 | FPL | Exploring Potential Benefits of 3D FPGA Integration. | Cristinel Ababei, Pongstorn Maidee, Kia Bazargan |
| 2003 | DAC | Fast timing-driven partitioning-based placement for island style FPGAs. | Pongstorn Maidee, Cristinel Ababei, Kia Bazargan |
| 2003 | DATE | Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. | Wonjoon Choi, Kia Bazargan |
| 2003 | DSD | HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. | Karthikeyan Bhasyam, Kia Bazargan |
| 2003 | FCCM | Linear Placement for Static / Dynamic Reconfiguration in JBits. | Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan |
| 2003 | ICCAD | Placement Method Targeting Predictability Robustness and Performance. | Cristinel Ababei, Kia Bazargan |
| 2003 | ICCAD | Incremental Placement for Timing Optimization. | Wonjoon Choi, Kia Bazargan |
| 2003 | VLSID | Timing Minimization by Statistical Timing hMetis-based Partitioning. | Cristinel Ababei, Kia Bazargan |
| 2002 | DAC | A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. | Jinghuan Chen, Jaekyun Moon, Kia Bazargan |
| 2002 | DATE | Statistical Timing Driven Partitioning for VLSI Circuits. | Cristinel Ababei, Kia Bazargan |
| 2002 | ICCAD | Multi-objective circuit partitioning for cutsize and path-based delay minimization. | Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis |
| 2001 | DAC | Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. | Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh |
| 2000 | FCCM | A C to Hardware/Software Compiler. | Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh |
| 2000 | ICCD | Fast Hierarchical Floorplanning with Congestion and Timing Control. | Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh |
| 1999 | RSP | 3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. | Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh |