| 2025 | ITC | Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion. | Cheng-En Chung, Jun-Han Jian, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang, Dong-Yi Chen |
| 2022 | ITC | Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks. | Yan-Fu Chen, Duo-Yao Kang, Kuen-Jong Lee |
| 2022 | VTS | Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. | Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy |
| 2020 | ETS | Efficient Prognostication of Pattern Count with Different Input Compression Ratios. | Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski |
| 2020 | ITC | Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. | Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada |
| 2019 | ITC | International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. | Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian |
| 2018 | ITC | Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. | Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy |
| 2017 | ITC | A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems. | Shuo-Lian Hong, Kuen-Jong Lee |
| 2016 | ASPDAC | A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. | Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin |
| 2016 | ASPDAC | Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults. | Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee |
| 2016 | ITC | An on-chip self-test architecture with test patterns recorded in scan chains. | Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte |
| 2016 | ITC | Output bit selection methodology for test response compaction. | Wei-Cheng Lien, Kuen-Jong Lee |
| 2016 | ITC | Transformation of multiple fault models to a unified model for ATPG efficiency enhancement. | Cheng-Hung Wu, Kuen-Jong Lee |
| 2015 | ASPDAC | An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. | Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu |
| 2015 | DATE | A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. | Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee |
| 2014 | ETS | Output-bit selection with X-avoidance using multiple counters for test-response compaction. | Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh |
| 2014 | ITC | An efficient diagnosis-aware pattern generation procedure for transition faults. | Kuen-Jong Lee, Cheng-Hung Wu |
| 2014 | VTS | An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model. | Cheng-Hung Wu, Kuen-Jong Lee, Wei-Cheng Lien |
| 2012 | ISCAS | Accumulator-based output selection for test response compaction. | Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Shih-Shiun Chien, Krishnendu Chakrabarty |
| 2009 | ITC | Tolerance of performance degrading faults for effective yield improvement. | Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee |
| 2008 | ISCAS | A hybrid self-testing methodology of processor cores. | Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee |
| 2008 | ITC | Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. | Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li |
| 2008 | SAC | A hybrid software-based self-testing methodology for embedded processor. | Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee |
| 2007 | DATE | Reduction of detected acceptable faults for yield improvement via error-tolerance. | Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer |
| 2006 | VTS | An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. | Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer |
| 2005 | ISCAS | An embedded processor based SOC test platform. | Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong |
| 2005 | ITC | A novel test methodology based on error-rate to support error-tolerance. | Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer |
| 2001 | ITC | A token scan architecture for low power testing. | Tsung-Chu Huang, Kuen-Jong Lee |
| 2000 | DATE | An on Chip ADC Test Structure. | Yun-Che Wen, Kuen-Jong Lee |
| 1999 | VTS | An Efficient BIST Method for Small Buffers. | Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee |
| 1998 | ICCAD | Using a single input to support multiple scan chains. | Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang |
| 1995 | DATE | Built-in intermediate voltage testing for CMOS circuits. | Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu |
| 1995 | ISCAS | A New Architecture for Analog Boundary Scan. | Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee |
| 1995 | ISCAS | An I | Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee |
| 1992 | DAC | SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer |
| 1992 | ITC | A Fast Testing Method for Sequential Circuits at the State Trasition Level. | Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee |
| 1991 | VTS | Constraints for using IDDQ testing to detect CMOS bridging faults. | Kuen-Jong Lee, Melvin A. Breuer |
| 1990 | ICCAD | A New Method for Assigning Signal Flow Directions to MOS Transistors. | Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer |
| 1990 | ITC | On the charge sharing problem in CMOS stuck-open fault testing. | Kuen-Jong Lee, Melvin A. Breuer |