| 2025 | DATE | Formally Verifying Analog Neural Networks with Device Mismatch Variations. | Yasmine Abu-Haeyeh, Thomas Bartelsmeier, Tobias Ladner, Matthias Althoff, Lars Hedrich, Markus Olbrich |
| 2024 | DAC | Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. | Kemal aglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler |
| 2024 | ITC | Identifying Undetectable Defects Using Equivalence Checking. | Lars Hedrich, Inga Abel, Jaafar Mejri, Vladimir A. Zivkovic |
| 2023 | DATE | Debugging Low Power Analog Neural Networks for Edge Computing. | Sascha Schmalhofer, Marwin Mller, Nikoletta Katsaouni, Marcel H. Schulz, Lars Hedrich |
| 2020 | ASPDAC | Establishing Reachset Conformance for the Formal Analysis of Analog Circuits. | Niklas Kochdumper, Ahmad Tarraf, Malgorzata Rechmal, Markus Olbrich, Lars Hedrich, Matthias Althoff |
| 2019 | DATE | Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata. | Ahmad Tarraf, Lars Hedrich |
| 2019 | ICMLA | Multi-agent Learning for Energy-Aware Placement of Autonomous Vehicles. | mer Ibrahim Erduran, Mirjam Minor, Lars Hedrich, Ahmad Tarraf, Frederik Ruehl, Hans Schroth |
| 2017 | DDECS | Novel metrics for Analog Mixed-Signal coverage. | Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher |
| 2016 | DATE | Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. | Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher |
| 2016 | FDL | Feature based state space coverage of analog circuits. | Andreas Furtig, Sebastian Steinhorst, Lars Hedrich |
| 2015 | DATE | Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores. | Julius von Rosen, Markus Meissner, Lars Hedrich |
| 2015 | DATE | Ageing simulation of analogue circuits and systems using adaptive transient evaluation. | Felix Salfelder, Lars Hedrich |
| 2013 | DAC | Modular system-level architecture for concurrent cell balancing. | Matthias Kauer, Swaminathan Naranayaswami, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty, Lars Hedrich |
| 2012 | DATE | Fast isomorphism testing for a graph-based analog circuit synthesis framework. | Markus Meissner, Oliver Mitea, Linda Luy, Lars Hedrich |
| 2012 | FDL | Analog assertion-based verification on partial state space representations using ASL. | Sebastian Steinhorst, Lars Hedrich |
| 2012 | ICCAD | Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuits. | Sebastian Steinhorst, Lars Hedrich |
| 2012 | ISORC | Detection and Defense Strategies against Attacks on an Artificial Hormone System Running on a Mixed Signal Chip. | Christoph Leineweber, Mathias Pacher, Benjamin Betting, Julius von Rosen, Uwe Brinkschulte, Lars Hedrich |
| 2011 | DATE | Automated constraint-driven topology synthesis for analog circuits. | Oliver Mitea, Markus Meissner, Lars Hedrich, P. Jores |
| 2011 | FDL | A machine-readable specification of analog circuits for integration into a validation flow. | Mingyu Ma, Lars Hedrich, Christian Sporrer |
| 2010 | DATE | Towards assertion-based verification of heterogeneous system designs. | Stefan Lmmermann, Jrgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Alexander Viehl, Alexander Jesser, Lars Hedrich |
| 2010 | ISCAS | Improving verification coverage of analog circuit blocks by state space-guided transient simulation. | Sebastian Steinhorst, Lars Hedrich |
| 2009 | DATE | Formal approaches to analog circuit verification. | Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang |
| 2008 | ASPDAC | A symbolic approach for mixed-signal model checking. | Alexander Jesser, Lars Hedrich |
| 2008 | DATE | Model Checking of Analog Systems using an Analog Specification Language. | Sebastian Steinhorst, Lars Hedrich |
| 2008 | DATE | Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. | Xiaoying Wang, Lars Hedrich |
| 2006 | ASPDAC | An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. | Xiaoying Wang, Lars Hedrich |
| 2006 | ISCAS | Hierarchical exploration and selection of transistor-topologies for analog circuit design. | Xiaoying Wang, Lars Hedrich |
| 2004 | DATE | Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. | Lutz Nthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke |
| 2002 | CAV | On Discrete Modeling and Model Checking for Nonlinear Analog Systems. | Walter Hartong, Lars Hedrich, Erich Barke |
| 2002 | DAC | Model checking algorithms for analog verification. | Walter Hartong, Lars Hedrich, Erich Barke |
| 2002 | DATE | An Approach to Model Checking for Nonlinear Analog Systems. | Walter Hartong, Lars Hedrich, Erich Barke |
| 2002 | DATE | Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. | Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke |
| 2002 | ICCAD | Analog circuit sizing based on formal methods using affine arithmetic. | Andreas C. Lemke, Lars Hedrich, Erich Barke |
| 2000 | DAC | A current driven routing and verification methodology for analog applications. | Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke |
| 1999 | CASC | On the Simplification of Nonlinear DAE Systems in Analog Circuit Design. | Tim Wichmann, Ralf Popp, Walter Hartong, Lars Hedrich |
| 1998 | DATE | A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. | Lars Hedrich, Erich Barke |
| 1996 | DAC | Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. | Carsten Borchers, Lars Hedrich, Erich Barke |
| 1995 | ICCAD | A formal approach to nonlinear analog circuit verification. | Lars Hedrich, Erich Barke |