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Laura Pozzi

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

37

Venues

13

Active years

1998–2026

Best venue rank

A*

Where they publish

Papers

37 indexed papers, newest first.

YearVenueTitleAuthors
2026DATETowards Input-Distribution-Aware Approximate Multiplier Generation for CNNs.Alessandro Buccolini, Marco Biasion, Rodrigo Otoni, George A. Constantinides, Laura Pozzi
2025DATEMonomorphism-Based CGRA Mapping Via Space and Time Decoupling.Cristian Tirelli, Rodrigo Otoni, Laura Pozzi
2024EuroParMapping Code on Coarse Grained Reconfigurable Arrays Using a SAT Solver.Cristian Tirelli, Laura Pozzi
2023DATESAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi
2023DSNA Parametrizable Template for Approximate Logic Synthesis.Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
2023DSNMulti-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits.Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
2022DATEINCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection.Lorenzo Ferretti, Giovanni Ansaloni, Renaud Marquis, Toms Teijeiro, Philippe Ryvlin, David Atienza, Laura Pozzi
2019DACPartition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits.Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
2019DATETailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors.Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi, Amir Aminifar, David Atienza, Leila Cammoun, Philippe Ryvlin
2019ICCDCompiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code.Georgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2018CASESA partitioning strategy for exploring error-resilience in circuits: work-in-progress.Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
2018DATECircuit carving: A methodology for the design of approximate hardware.Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
2018ICCDLattice-Traversing Design Space Exploration for High Level Synthesis.Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
2018ISCASHeterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications.Soumya Basu, Loris Duch, Miguel Pen-Quirs, David Atienza, Giovanni Ansaloni, Laura Pozzi
2011DATESlack-aware scheduling on Coarse Grained Reconfigurable Arrays.Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt
2009DATEHeterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration.Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
2008CASESCompiling custom instructions onto expression-grained reconfigurable architectures.Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
2007DATEPolynomial-time subgraph enumeration for automated instruction set extension.Paolo Bonzini, Laura Pozzi
2007DATEA future of customizable processors: are we there yet?Laura Pozzi, Pierre G. Paulin
2006CASESCode transformation strategies for extensible embedded processors.Paolo Bonzini, Laura Pozzi
2006DATEAutomatic identification of application-specific functional units with architecturally visible storage.Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2006DATECombining algorithm exploration with instruction set design: a case study in elliptic curve cryptography.Johann Groschdl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma
2006VLSIDPerformance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2005CASESExploiting pipelining to relax register-file port constraints of instruction-set extensions.Laura Pozzi, Paolo Ienne
2005DATEISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2004DACIntroduction of local memory elements in instruction set extensions.Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt
2004DACVirtual memory window for application-specific reconfigurable coprocessors.Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004DATEOperating System Support for Interface Virtualisation of Reconfigurable Coprocessors.Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne
2004FCCMVirtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004FPLDynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004SCOPESAutomatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne
2003DACAutomatic application-specific instruction-set extensions under microarchitectural constraints.Kubilay Atasu, Laura Pozzi, Paolo Ienne
2002DATEAutomatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors.Laura Pozzi, Miljan Vuletic, Paolo Ienne
2001RSPDetermining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
2000FPGADetermining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
1999DATEA DAG-Based Design Approach for Reconfigurable VLIW Processors.Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
1998FPGAMinimizing the Application Time for Manufacturer Testing of FPGA (Abstract).Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami