| 2005 | ITC | An optimal test pattern selection method to improve the defect coverage. | Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer |
| 2004 | DATE | Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. | Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer |
| 2004 | VTS | Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. | Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer |
| 2003 | ITC | Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. | Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir |
| 2002 | DAC | Enhancing test efficiency for delay fault testing using multiple-clocked schemes. | Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams |
| 2002 | DATE | Directed-Binary Search in Logic BIST Diagnostics. | Rohit Kapur, Thomas W. Williams, M. Ray Mercer |
| 2002 | DATE | A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. | Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer |
| 2002 | ITC | Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. | Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams |
| 2000 | ITC | Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. | Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer |
| 1999 | ICCD | Multi-Level Logic Minimization through Fault Dictionary Analysis. | Ronald W. Mehler, M. Ray Mercer |
| 1999 | ITC | Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. | Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer |
| 1999 | VTS | REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. | Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer |
| 1996 | DATE | Iddq Testing for High Performance CMOS - The Next Ten Years. | Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly |
| 1996 | ICCD | Using Functional Information and Strategy Switching in Sequential ATPG. | Jaehong Park, M. Ray Mercer |
| 1996 | ICCD | A Better ATPG Algorithm and Its Design Principles. | Li-C. Wang, M. Ray Mercer, Thomas W. Williams |
| 1996 | ITC | Using Target Faults To Detect Non-Tartget Defects. | Li-C. Wang, M. Ray Mercer, Thomas W. Williams |
| 1996 | ITC | I | Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly |
| 1995 | DATE | Improved sequential ATPG using functional observation information and new justification methods. | Jaehong Park, Chanhee Oh, M. Ray Mercer |
| 1995 | DATE | Enhanced testing performance via unbiased test sets. | Li-C. Wang, M. Ray Mercer, Thomas W. Williams |
| 1995 | ITC | On Efficiently and Reliably Achieving Low Defective Part Levels. | Li-C. Wang, M. Ray Mercer, Thomas W. Williams |
| 1995 | VTS | On the decline of testing efficiency as fault coverage approaches 100%. | Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams |
| 1994 | VTS | Limitations in predicting defect level based on stuck-at fault coverage. | Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams |
| 1993 | ICCD | An Efficient Symbolic Design Verification System. | Jaehong Park, M. Ray Mercer |
| 1993 | ITC | Switch-Level ATPG Using Constraint-Guided Line Justification. | Eun Sei Park, M. Ray Mercer |
| 1993 | VTS | Combinational circuit ATPG using binary decision diagrams. | Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer |
| 1992 | DAC | Functional Approaches to Generating Orderings for Efficient Symbolic Representations. | M. Ray Mercer, Rohit Kapur, Don E. Ross |
| 1992 | ICCAD | ETA: electrical-level timing analysis. | Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage |
| 1992 | ICCD | A Synthesis Algorithm for Two-Level XOR Based Circuits. | Mark A. Heap, William A. Rogers, M. Ray Mercer |
| 1992 | ITC | All Tests for a Fault Are Not Equally Valuable for Defect Detection. | Rohit Kapur, Jaehong Park, M. Ray Mercer |
| 1992 | VTS | The roles of controllability and observability in design for test. | Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross |
| 1991 | DAC | Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. | Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer |
| 1991 | DAC | The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. | Thomas W. Williams, Bill Underwood, M. Ray Mercer |
| 1991 | ITC | Delay Testing Quality in Timing-Optimized Designs. | Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer |
| 1990 | DAC | The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. | Kenneth M. Butler, M. Ray Mercer |
| 1990 | DAC | An Efficient Delay Test Generation System for Combinational Logic Circuits. | Eun Sei Park, M. Ray Mercer |
| 1989 | DAC | A Deterministic Approach to Adjacency Testing for Delay Faults. | C. Thomas Glover, M. Ray Mercer |
| 1988 | DAC | CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. | Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler |
| 1988 | DAC | A Method of Delay Fault Test Generation. | C. Thomas Glover, M. Ray Mercer |
| 1988 | ITC | Statistical Delay Fault Coverage and Defect Level for Delay Faults. | Eun Sei Park, Thomas W. Williams, M. Ray Mercer |
| 1988 | ITC | D^3FS: A Demand Driven Deductive Fault Simulator. | Steven P. Smith, Bill Underwood, M. Ray Mercer |
| 1987 | DAC | A Topological Search Algorithm for ATPG. | Tom E. Kirkland, M. Ray Mercer |
| 1987 | DAC | Demand Driven Simulation: BACKSIM. | Steven P. Smith, M. Ray Mercer, B. Brodk |
| 1986 | ITC | Deterministic Versus Random Testing. | Vishwani D. Agrawal, M. Ray Mercer |
| 1986 | ITC | Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. | Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood |
| 1986 | ITC | Informed Test Generation Guidance Using Partially Specified Fanout Constraints. | Ki Soo Hwang, M. Ray Mercer |
| 1986 | ITC | Logic Elements for Universally Testable Circuits. | M. Ray Mercer |
| 1985 | DAC | CADTOOLS: a CAD algorithm development system. | Eric Schell, M. Ray Mercer |
| 1985 | ITC | Built-In Self Test Input Generator for Programmable Logic Arrays. | John Salick, Bill Underwood, M. Ray Mercer |
| 1984 | ITC | Correlating Testability with Fault Detection. | Bill Underwood, M. Ray Mercer |
| 1983 | ITC | Testing Issues at the University of Texas. | M. Ray Mercer |
| 1982 | ITC | Testability Measures : What Do They Tell Us ? | Vishwani D. Agrawal, M. Ray Mercer |
| 1981 | ITC | Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. | M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman |