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Madhura Purnaprajna

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

15

Venues

7

Active years

2008–2025

Best venue rank

National

Where they publish

Papers

15 indexed papers, newest first.

YearVenueTitleAuthors
2025HiPCMATANALYZE - A Custom Accelerator Generator for Sparse Dense and Dense Sparse Matrix Multiplication.Mohammed Sahel, Disha Kiran D, M. R. Ashuthosh, Madhura Purnaprajna
2025HiPCPARISCV: A RISC-V Profiler for Application-Specific Hardware Optimization.Spoorthi S, M. R. Ashuthosh, Bharadhwaj K, Vinay Reddy, Madhura Purnaprajna
2025VLSIDOptimization of Sub-Threshold Standard Cells for Energy Efficient Designs.Vardhan Suroshi, Karthik B. K, Vikram Kannur, Vinay Reddy, Madhura Purnaprajna
2022VLSIDMAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication.M. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan, Madhura Purnaprajna
2021VLSIDDemystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis.Remya Ramakrishnan, Aditya K. V. Dev, Darshik A. S, Renuka Chinchwadkar, Madhura Purnaprajna
2020FCCMGbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications.Oscar Ferraz, Srinivasan Subramaniyan, Guohui Wang, Joseph R. Cavallaro, Gabriel Falco, Madhura Purnaprajna
2019VLSIDk-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics.Simmi M. Bose, Varsha S. Lalapura, S. Saravanan, Madhura Purnaprajna
2018CASESPerformance modeling for data distribution in heterogeneous computing systems: work in progress.Vanishree K, Madhura Purnaprajna
2018VLSIDTileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs.Sahu Sai Vikram, Vibha Panty, Mihir Mody, Madhura Purnaprajna
2015FPLEnabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions.Meena Belwal, Madhura Purnaprajna, T. S. B. Sudarshan
2013FCCMA Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers.Madhura Purnaprajna, Paolo Ienne
2013FPGAShadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only).Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2013FPLShadow And-Inverter Cones.Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2012FCCMShortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.Gabriel Falco, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
2008DATEPower Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography.Madhura Purnaprajna, Christoph Puttmann, Mario Porrmann