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Mark Kassab

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

26

Venues

4

Active years

1995–2022

Best venue rank

A*

Where they publish

Papers

26 indexed papers, newest first.

YearVenueTitleAuthors
2022VTSAccurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
2020ETSEfficient Prognostication of Pattern Count with Different Input Compression Ratios.Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
2020ITCStreaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs.Jean-Franois Ct, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Coln-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant
2020ITCPrediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
2020VTSEffective Design of Layout-Friendly EDT Decompressor.Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer
2014ETSUsing dynamic shift to reduce test data volume in high-compression designs.Xijiang Lin, Mark Kassab, Janusz Rajski
2014ITCIsometric test compression with low toggling activity.Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2013ITCEDT bandwidth management - Practical scenarios for large SoC designs.Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2011ITCEDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2011ITCA novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab
2010ITCDynamic channel allocation for higher EDT compression in SoC designs.Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2010ITCLow capture power at-speed test in EDT environment.Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab
2010ITCClock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab
2010VTSAt-speed scan test with low switching activity.Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab
2008ITCLow Power Scan Shift and Capture in the EDT Environment.Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2007DACTest Generation in the Presence of Timing Exceptions and Constraints.Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
2006ITCOCI: Open Compression Interface.Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
2006ITCX-Press Compactor for 1000x Reduction of Test Data.Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2004ITCAffordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski
2004ITCRealizing High Test Quality Goals with Smart Test Resource Usage.Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
2003ITCIndustrial Experience with Adoption of EDT for Low-Cost Test without Concessions.Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
2002ITCEmbedded Deterministic Test for Low-Cost Manufacturing Test.Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
1999ITCLogic BIST for large industrial designs: real issues and case studies.Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
1998DACA Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
1995DACSoftware Accelerated Functional Fault Simulation for Data-Path Architectures.Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1995ITCHierarchical Functional-Fault Simulation for High-Level Synthesis.Mark Kassab, Janusz Rajski, Jerzy Tyszer