| 2017 | ASPDAC | Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface. | Masaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jrgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez |
| 2013 | APNOMS | Error analysis of an estimation method using RTT for available bandwidth of a bottleneck link. | Masaharu Imai, Takayuki Ozawa, Yoshio Sugizaki, Koichi Asatani |
| 2011 | ASPDAC | Biological information sensing technologies for medical, health care, and wellness applications. | Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato |
| 2010 | ASPDAC | A new compilation technique for SIMD code generation across basic block boundaries. | Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai |
| 2010 | ISCAS | Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. | Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2009 | ASPDAC | Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. | Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2007 | ASPDAC | A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. | Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2007 | ICASSP | A Block-Floating-Point Processor for Rapid Application Development. | Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi |
| 2005 | ASPDAC | Enabling RTOS simulation modeling in a system level design language. | M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2005 | DATE | RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. | M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2004 | ASPDAC | Synthesizable HDL generation method for configurable VLIW processors. | Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2004 | DATE | Architecture-Level Performance Estimation for IP-Based Embedded Systems. | Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2004 | ISCAS | S-sequence: a new floorplan representation method preserving room abutment relationships. | Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai |
| 2003 | ICASSP | Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. | Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai |
| 2003 | SCOPES | A Code Selection Method for SIMD Processors with PACK Instructions. | Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai |
| 2002 | ICASSP | Design space exploration for DSP applications using the ASIP development system PEAS-III. | Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai |
| 2002 | RSP | Design of Application Specific CISC Using PEAS-III. | Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai |
| 2001 | ASPDAC | Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. | Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai |
| 2000 | ASPDAC | One language or more?: how can we design an SoC at a system level? | Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura |
| 2000 | ICCD | PEAS-III: An ASIP Design Environment. | Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi |
| 1999 | ICASSP | A programmable processor with multiple functional units and banked registers for general purpose numerical processing. | Takafumi Morifuji, Yoshinori Takeuchi, Masaharu Imai |
| 1998 | ASPDAC | A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. | Nguyen-Ngoc Bnh, Masaharu Imai, Yoshinori Takeuchi |
| 1997 | ASPDAC | VLSI implementation of a real-time operating system. | Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai |
| 1996 | DAC | A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. | Nguyen-Ngoc Bnh, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi |
| 1995 | ASPDAC | A hardware/software codesign method for pipelined instruction set processor using adaptive database. | Nguyen-Ngoc Bnh, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi |
| 1995 | ASPDAC | Future direction of synthesizability and interoperability of HDL's: part 1. | Masaharu Imai, Eugenio Villar |
| 1995 | ASPDAC | Future direction of synthesizabilty and interoperability of HDL's: part 2. | Eugenio Villar, Masaharu Imai |
| 1993 | ICCAD | An ASIP instruction set optimization algorithm with functional module sharing constraint. | Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi |
| 1991 | ICCD | An Integrated Design Environment for Application Specific Integrated Processor. | Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi |
| 1984 | ICDCS | The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System. | Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura |
| 1979 | IJCAI | A Parallel Searching Scheme for Multiprocessor Systems and Its Application to Combinatorial Problems. | Masaharu Imai, Yuuji Yoshida, Teruo Fukumura |