| 2019 | IOLTS | Error Correction Coding of Stochastic Numbers Using BER Measurement. | Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa |
| 2019 | ISCAS | Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. | Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi |
| 2018 | IOLTS | Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
| 2018 | IOLTS | An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. | Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa |
| 2018 | ISCAS | A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
| 2018 | SiggraphA | Gesture recognition of air-tapping and its application to character input in VR space. | Mamoru Hirota, Ayumu Tsuboi, Masayuki Yokoyama, Masao Yanagisawa |
| 2017 | IOLTS | Hardware Trojans classification for gate-level netlists using multi-layer neural networks. | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
| 2017 | IOLTS | Hardware Trojan detection and classification based on steady state learning. | Masaru Oya, Masao Yanagisawa, Nozomu Togawa |
| 2017 | ISCAS | Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
| 2017 | ISCAS | Effective write-reduction method for MLC non-volatile memory. | Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa |
| 2017 | SiggraphA | A proposal for wearable controller device and finger gesture recognition using surface electromyography. | Ayumu Tsuboi, Mamoru Hirota, Junki Sato, Masayuki Yokoyama, Masao Yanagisawa |
| 2016 | IOLTS | Hardware Trojans classification for gate-level netlists based on machine learning. | Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa |
| 2016 | IOLTS | Redesign for untrusted gate-level netlists. | Masaru Oya, Masao Yanagisawa, Nozomu Togawa |
| 2016 | ISCAS | Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. | Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa |
| 2015 | ASPDAC | A bit-write reduction method based on error-correcting codes for non-volatile memories. | Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa |
| 2015 | DATE | A score-based classification method for identifying hardware-trojans at gate-level netlists. | Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2015 | ICCAD | Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. | Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa |
| 2015 | ISCAS | A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. | Kotaro Terada, Masao Yanagisawa, Nozomu Togawa |
| 2014 | ISCAS | Scan-based attack on the LED block cipher using scan signatures. | Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa |
| 2014 | ISCAS | Linear and bi-linear interpolation circuits using selector logics and their evaluations. | Masashi Shio, Masao Yanagisawa, Nozomu Togawa |
| 2013 | ISCAS | Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. | Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2013 | ISCAS | A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. | Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa |
| 2013 | PRDC | Secure Scan Design with Dynamically Configurable Connection. | Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2012 | ISCAS | An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. | Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa |
| 2010 | ASPDAC | Scan-based attack against elliptic curve cryptosystems. | Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2010 | ISCAS | State-dependent changeable scan architecture against scan-based side channel attacks. | Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2010 | ISCAS | Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. | Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2009 | ASPDAC | Exact and fast L1 cache simulation for embedded systems. | Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2009 | ITC | Design-for-secure-test for crypto cores. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2008 | ASPDAC | GECOM: Test data compression combined with all unknown response masking. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2008 | ASPDAC | Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 | Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2007 | ISCAS | Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2006 | ASPDAC | An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. | Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2006 | ASPDAC | FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. | Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2005 | ASPDAC | A processor core synthesis system in IP-based SoC design. | Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2005 | ISCAS | Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. | Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | A cosynthesis algorithm for application specific processors with heterogeneous datapaths. | Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | Instruction set and functional unit synthesis for SIMD processor cores. | Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | A thread partitioning algorithm in low power high-level synthesis. | Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2003 | ASPDAC | A hardware/software partitioning algorithm for SIMD processor cores. | Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2002 | VLSID | VLSI Architecture for a Flexible Motion Estimation with Parameters. | Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2001 | ASPDAC | Area/delay estimation for digital signal processor cores. | Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2000 | ASPDAC | An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). | Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1999 | ASPDAC | A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. | Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1998 | ASPDAC | A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. | Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1998 | ASPDAC | An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. | Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki |