Maurizio Palesi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
46
Venues
18
Active years
2002–2026
Best venue rank
A*
Where they publish
Papers
46 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Multi-Partner Project: Outcomes of the ICSC Flagship 2 Project on Architectures and Design Methodologies to Accelerate AI Workloads. | Cristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Cristian Zambelli, Sebastiano Fabio Schifano, Francesco Conti, Angelo Garofalo, Luca Benini, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri, Fabio Frustaci |
| 2025 | ASPDAC | A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference. | Pol Puigdemont, Enrico Russo, Axel Wassington, Abhijit Das, Sergi Abadal, Maurizio Palesi |
| 2025 | DATE | Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement Learning. | Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2025 | PDP | An Anomaly Detection Model for RISC-V in Automotive Applications: A Domain-Specific Accelerator Perspective. | Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia |
| 2025 | QCE | On the Impact of Classical and Quantum Communication Networks Upon Modular Quantum Computing Architecture System Performance. | Pau Escofet, Abhijit Das, Sahar Ben Rached, Santiago Rodrigo, Jordi Domingo, Fabio Sebastiano, Masoud Babaie, Batuhan Keskin, Edoardo Charbon, Peter Haring Bolvar, Maurizio Palesi, Elena Blokhina, Robert Bogdan Staszewski, Avishek Nag, Artur Garca-Sez, Sergi Abadal, Eduard Alarcn, Carmen G. Almudver |
| 2025 | QCE | TeleSABRE: Heuristic Layout Synthesis in Multi-Core Quantum Systems with Teleport Interconnect. | Enrico Russo, Elio Vinciguerra, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2024 | DAC | A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. | Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2024 | ICINCO | Characteristics-Based Least Common Multiple: A Novel Clustering Algorithm to Optimize Indoor Positioning. | Hamaad Rafique, Davide Patti, Maurizio Palesi, Gaetano Carmelo La Delfa |
| 2024 | IPIN | Fusing Visuals with Magnetic Signals to Improve Indoor Localization Using Vision Transformer. | Hamaad Rafique, Davide Patti, Maurizio Palesi, Gaetano Carmelo La Delfa |
| 2024 | ISCAS | Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. | Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania |
| 2023 | ISCAS | Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. | Eduard Alarcn, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolvar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur Garca-Sez, Carmen G. Almudver |
| 2022 | DATE | MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. | Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2021 | PERCOM | LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. | Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
| 2020 | AINA | Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs. | Sirine Mnejja, Yassine Aydi, Mohamed Abid, Salvatore Monteleone, Maurizio Palesi, Davide Patti |
| 2020 | DSD | DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. | Habiba Lahdhiri, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Jordane Lorandel, Emmanuelle Bourdel, Vincenzo Catania |
| 2020 | DSD | Efficient Compression Technique for NoC-based Deep Neural Network Accelerators. | Jordane Lorandel, Habiba Lahdhiri, Emmanuelle Bourdel, Salvatore Monteleone, Maurizio Palesi |
| 2019 | DATE | ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. | Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Terrence S. T. Mak |
| 2019 | MICRO | Study on logic-based routing for 3D NOCs. | Minghua Tang, Maurizio Palesi |
| 2019 | VLSID | Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. | Dipika Deb, John Jose, Maurizio Palesi |
| 2016 | DATE | Energy efficient transceiver in wireless Network on Chip architectures. | Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti |
| 2016 | MICRO | Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC. | Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono, Maurizio Palesi |
| 2016 | PDP | Efficient Congestion-Aware Scheme for Wireless on-Chip Networks. | Amin Rezaei, Masoud Daneshtalab, Maurizio Palesi, Danella Zhao |
| 2015 | DATE | A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. | Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono |
| 2014 | DAC | SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. | Mohammad Fattah, Maurizio Palesi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2014 | DATE | An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. | Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania |
| 2014 | DATE | Adaptive power allocation for many-core systems inspired from multiagent auction model. | Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi |
| 2014 | ISCA | A Closed Loop Control based Power Manager for WiNoC Architectures. | Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono |
| 2013 | DSD | An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. | Giuseppe Ascia, Maurizio Palesi, Vincenzo Catania |
| 2013 | DSD | Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. | Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania |
| 2013 | HPCC | Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. | Andrea Mineo, Marina Masi, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania |
| 2011 | DATE | Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. | Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi |
| 2011 | NPC | Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. | Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu |
| 2010 | DSD | An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. | Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania |
| 2010 | EuroPar | A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms. | Rickard Holsmark, Shashi Kumar, Maurizio Palesi |
| 2009 | DSD | An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. | Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales |
| 2009 | DSD | Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. | Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania |
| 2008 | DSD | High Performance Computing for Embedded System Design: A Case Study. | Vincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti |
| 2008 | DSD | Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. | Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania |
| 2008 | EuroPar | A Communication-Aware Topological Mapping Technique for NoCs. | Rafael Tornero, Juan M. Ordua, Maurizio Palesi, Jos Duato |
| 2006 | CEC | A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti |
| 2006 | DSD | Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. | Rickard Holsmark, Maurizio Palesi, Shashi Kumar |
| 2005 | ASPDAC | A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
| 2005 | CEC | An evolutionary approach to network-on-chip mapping problem. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi |
| 2005 | ISCAS | Hyperblock formation: a power/energy perspective for high performance VLIW architectures. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
| 2003 | CEC | An evolutionary approach for reducing the switching activity in address buses. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato |
| 2002 | VLSID | A Framework for Design Space Exploration of Parameterized VLSI Systems. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi |