| 2026 | DATE | DyGen: A Constant-Time Kernel Generator for Dynamic-Shape Neural Networks. | Yuhan Kang, Wenrui Zhang, Dong Chen, Yang Shi, Jianchao Yang, Zeyu Xue, Jing Feng, Mei Wen |
| 2026 | ISCA | Harmonia: A Unified Hierarchical Scheduling Framework for Sparse Matrix Multiplication. | Jingkui Yang, Fangxin Liu, Xin Ju, Ning Yang, Chenyang Guan, Junjie Wang, Zongwu Wang, Mei Wen, Jian Liu, Li Jiang, Haibing Guan |
| 2025 | DATE | WinAcc: Window-based Acceleration of Neural Networks Using Block Floating Point. | Xin Ju, Jun He, Mei Wen, Jing Feng, Yasong Cao, Junzhong Shen, Zhaoyun Chen, Yang Shi |
| 2025 | DATE | SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level Sparsity. | Jingkui Yang, Mei Wen, Junzhong Shen, Jianchao Yang, Yasong Cao, Jun He, Minjin Tang, Zhaoyun Chen, Yang Shi |
| 2025 | EMNLP | SwiftPrune: Hessian-Free Weight Pruning for Large Language Models. | Yuhan Kang, Yang Shi, Mei Wen, Jun He, Jianchao Yang, Zeyu Xue, Jing Feng, Xinwang Liu |
| 2025 | ICPP | SmartBlock: Adaptive Block Floating Point Quantization for Efficient DNN Acceleration. | Xin Ju, Jingkui Yang, Mei Wen, Jun He, Jing Feng, Minjin Tang, Zhaoyun Chen, Yang Shi |
| 2025 | ISCAS | Super Microscaling: Enhancing Precision and Hardware Efficiency in Deep Learning Quantization. | Jing Feng, Zhuang Cao, Xin Ju, Mei Wen, Yang Guo |
| 2025 | ISCAS | CAMO: A High-Performance CIM-based Lightweight CNN Accelerator for Mobile Devices. | Xin Ju, Renyu Yang, Mei Wen, Junzhong Shen, Tianyu Wang, Zhaoyan Shen, Zili Shao, Bin Liang |
| 2024 | ICA3PP | MAP-SIM: A Performance Model for Shared-Memory Heterogeneous Systems with Mapping Awareness. | Yuhang Li, Mei Wen, Junzhong Shen, Zhaoyun Chen, Yang Shi |
| 2024 | ICA3PP | MSA | Minjin Tang, Mei Wen, Junzhong Shen, Jingkui Yang, Zeyu Xue, Zili Shao |
| 2024 | ISCAS | Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency. | Jing Feng, Mei Wen, Xin Ju, Junzhong Shen, Yang Guo |
| 2024 | MICRO | HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs. | Jianchao Yang, Mei Wen, Dong Chen, Zhaoyun Chen, Zeyu Xue, Yuhang Li, Junzhong Shen, Yang Shi |
| 2023 | DAC | Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs. | Xiaolei Zhao, Zhaoyun Chen, Yang Shi, Mei Wen, Chunyun Zhang |
| 2023 | ICCD | Releasing the Potential of Tensor Core for Unstructured SpMM using Tiled-CSR Format. | Zeyu Xue, Mei Wen, Zhaoyun Chen, Yang Shi, Minjin Tang, Jianchao Yang, Zhongdi Luo |
| 2022 | ASPDAC | Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling. | Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen |
| 2022 | HPCC | MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. | Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei |
| 2022 | HPCC | CORF: Bridging the Gap of Complex Operator Fusion for Faster DNN Inference. | Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen |
| 2022 | ICCD | BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. | Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang |
| 2022 | ICPP | Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. | Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu |
| 2022 | ISCAS | S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness. | Yuhang Li, Mei Wen, Renyu Yang, Junzhong Shen, Yasong Cao, Jianan Wang |
| 2022 | ISPASS | TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation. | Yuhang Li, Mei Wen, Jiawei Fei, Junzhong Shen, Yasong Cao |
| 2021 | HPCC | Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators. | Renyu Yang, Junzhong Shen, Mei Wen, Yasong Cao, Yuhang Li |
| 2021 | HPCC | SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. | Jianchao Yang, Mei Wen, Minjin Tang, Junzhong Shen, Chunyuan Zhang |
| 2021 | ICPP | sRouting: Towards a Better Flow Size Estimation Performance through Routing and Sketch Configuration. | Yang Shi, Mei Wen |
| 2020 | DAC | Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. | Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang |
| 2020 | FPGA | Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. | Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang |
| 2020 | ICA3PP | Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform. | Qixuan Cheng, Mei Wen, Junzhong Shen, Deguang Wang, Chunyuan Zhang |
| 2020 | ICA3PP | Optimized HybridSketch: More Efficient with Analysis and Algorithm. | Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang |
| 2020 | ICPP | Towards High-Efficiency Data Centers via Job-Aware Network Scheduling. | Yang Shi, Mei Wen, Chunyuan Zhang |
| 2020 | ISCC | Incremental Deployment of Programmable Switches for Sketch-based Network Measurement. | Yang Shi, Mei Wen, Chunyuan Zhang |
| 2019 | DAC | Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. | Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang |
| 2019 | DATE | GENIE: QoS-guided Dynamic Scheduling for CNN-based Tasks on SME Clusters. | Zhaoyun Chen, Lei Luo, Haoduo Yang, Jie Yu, Mei Wen, Chunyuan Zhang |
| 2019 | FPGA | Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. | Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang |
| 2019 | HPCC | SACC: Configuring Application-Level Cache Intelligently for In-Memory Database Based on Long Short-Term Memory. | Jiawei Fei, Yang Shi, Mei Wen, Chunyuan Zhang |
| 2019 | HPCC | TBSW: Time-Based Sliding Window Algorithm for Network Traffic Measurement. | Zijun Hang, Yang Shi, Mei Wen, Chunyuan Zhang |
| 2019 | HPCC | Metaflow: A Better Traffic Abstraction for Distributed Applications. | Yang Shi, Jiawei Fei, Mei Wen, Qun Huang, Nan Wu |
| 2019 | ICPP | An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform. | Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang |
| 2019 | INFOCOM | Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA. | Zhuang Cao, Huayou Su, Qianming Yang, Mei Wen, Chunyuan Zhang |
| 2019 | INFOCOM | Poster Abstract: Deep Learning Workloads Scheduling with Reinforcement Learning on GPU Clusters. | Zhaoyun Chen, Lei Luo, Wei Quan, Mei Wen, Chunyuan Zhang |
| 2019 | ISCAS | Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. | Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang |
| 2019 | ISCC | KVSwitch: An In-network Load Balancer for Key-Value Stores. | Yang Shi, Jiawei Fei, Mei Wen, Chunyuan Zhang |
| 2018 | FPGA | Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. | Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang |
| 2018 | HPCC | Multiple CNN-based Tasks Scheduling across Shared GPU Platform in Research and Development Scenarios. | Zhaoyun Chen, Lei Luo, Wei Quan, Yang Shi, Jie Yu, Mei Wen, Chunyuan Zhang |
| 2018 | ISCAS | Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. | Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang |
| 2017 | NPC | Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. | Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang |
| 2016 | ICPADS | Enabling Tissue-Scale Cardiac Simulations Using Heterogeneous Computing on Tianhe-2. | Johannes Langguth, Qiang Lan, Namit Gaur, Xing Cai, Mei Wen, Chunyuan Zhang |
| 2015 | BMVC | Enable Scale and Aspect Ratio Adaptability in Visual Tracking with Detection Proposals. | Dafei Huang, Lei Luo, Mei Wen, Zhaoyun Chen, Chunyuan Zhang |
| 2015 | ICA3PP | Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. | Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen |
| 2015 | ICIP | Fast tracking via context depth model learning. | Zhaoyun Chen, Lei Luo, Mei Wen, Chunyuan Zhang |
| 2014 | EuroPar | Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs. | Dafei Huang, Mei Wen, Changqing Xun, Dong Chen, Xing Cai, Yuran Qiao, Nan Wu, Chunyuan Zhang |
| 2014 | ICA3PP | Utilizing Multiple Xeon Phi Coprocessors on One Compute Node. | Xinnan Dong, Jun Chai, Jing Yang, Mei Wen, Nan Wu, Xing Cai, Chunyuan Zhang, Zhaoyun Chen |
| 2013 | HPCC | Automatic Mapping Single-Device OpenCL Program to Heterogeneous Multi-device Platform. | Dong Chen, Changqing Xun, Dafei Huang, Mei Wen, Chunyuan Zhang |
| 2013 | HPCC | Solving the Cardiac Model Using Multi-core CPU and Many Integrated Cores (MIC). | Jing Yang, Jun Chai, Mei Wen, Nan Wu, Chunyuan Zhang |
| 2013 | ICCS | Performance of Sediment Transport Simulations on NVIDIA's Kepler Architecture. | Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai |
| 2013 | ICPADS | On the GPU-CPU Performance Portability of OpenCL for 3D Stencil Computations. | Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai |
| 2012 | CLUSTER | Using 1000+ GPUs and 10000+ CPUs for Sedimentary Basin Simulations. | Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai, Chunyuan Zhang |
| 2012 | FPGA | The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). | Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao |
| 2012 | FPL | Extending BORPH for shared memory reconfigurable computers. | Changqing Xun, Mei Wen, Nan Wu, Chunyuan Zhang, Hayden Kwok-Hay So |
| 2012 | ICPADS | A Parallel H.264 Encoder with CUDA: Mapping and Evaluation. | Nan Wu, Mei Wen, Huayou Su, Ju Ren, Chunyuan Zhang |
| 2012 | PDCAT | Improving Performance of GPU Specific OpenCL Program on CPUs. | Qiang Lan, Changqing Xun, Mei Wen, Huayou Su, Lifang Liu, Chunyuan Zhang |
| 2011 | ICIG | A Multilevel Parallel Intra Coding for H.264/AVC Based on CUDA. | Huayou Su, Nan Wu, Chunyuan Zhang, Mei Wen, Ju Ren |
| 2010 | DSD | Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. | Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang |
| 2009 | HiPC | Cache streamization for high performance stream processor. | Nan Wu, Mei Wen, Ju Ren, Yi He, Changqing Xun, Wei Wu, Chunyuan Zhang |
| 2008 | ASPDAC | Load scheduling: Reducing pressure on distributed register files for free. | Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang |
| 2007 | HiPC | FT64: Scientific Computing with Streams. | Mei Wen, Nan Wu, Chunyuan Zhang, Wei Wu, Qianming Yang, Changqing Xun |
| 2004 | ISPA | A Parallel Reed-Solomon Decoder on the Imagine Stream Processor. | Mei Wen, Chunyuan Zhang, Nan Wu, Haiyan Li, Li Li |