| 2026 | VTS | IABIST: An IJTAG-Compliant Machine Learning-Based Analog BIST Framework for SoC Verification. | Jules Kouamo, Emmanuel Simeu, Michele Portolan |
| 2025 | IOLTS | Machine Learning-Based Parametric Fault Detection in Analog and Mixed-Signal Circuits. | Jules Kouamo, Emmanuel Simeu, Michele Portolan |
| 2024 | ETS | What Would Interactive Testing With 1687 Look Like? | Michele Portolan, Martin Keim, J. F. Cot, Hans-Martin Von Staud |
| 2023 | VTS | Refreshing the JTAG Family. | Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg |
| 2022 | ITC | IEEE P1687.1: Extending the Network Boundaries for Test. | Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo |
| 2022 | ITC | Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure. | Michele Portolan, Antonios Pavlidis, Giorgio Di Natale, Eric Faehn, Haralampos-G. Stratigopoulos |
| 2021 | ETS | Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. | Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim |
| 2021 | ITC | Security EDA Extension through P1687.1 and 1687 Callbacks. | Michele Portolan, Vincent Reynaud, Paolo Maistri, Rgis Leveugle, Giorgio Di Natale |
| 2020 | ETS | Linking Chip, Board, and System Test via Standards. | Michele Portolan, Jeff Rearick, Martin Keim |
| 2020 | ETS | Dynamic Authentication-Based Secure Access to Test Infrastructure. | Michele Portolan, Vincent Reynaud, Paolo Maistri, Rgis Leveugle |
| 2020 | IOLTS | A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. | Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragn, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Rgis Leveugle, Salvador Mir |
| 2020 | ITC | New Perspectives on Core In-field Path Delay Test. | Riccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan |
| 2020 | ITC | Modeling Novel Non-JTAG IEEE 1687-Like Architectures. | Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick |
| 2019 | ETS | A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks. | Michele Portolan, Riccardo Cantoro, Ernesto Snchez |
| 2019 | ETS | Alternatives to Fault Injections for Early Safety/Security Evaluations. | Michele Portolan, Alessandro Savino, Rgis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale |
| 2019 | ETS | Approximate computing design exploration through data lifetime metrics. | Alessandro Savino, Michele Portolan, Rgis Leveugle, Stefano Di Carlo |
| 2019 | ITC | Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. | Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Snchez, Giovanni Squillero, Anton Tsertov |
| 2017 | ETS | Mixed-signal BIST computation offloading using IEEE 1687. | Michele Portolan, Manuel J. Barragn, Rshdee Alhakim, Salvador Mir |
| 2017 | IOLTS | Reliability of computing systems: From flip flops to variables. | Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Rgis Leveugle |
| 2016 | ETS | A novel test generation and application flow for functional access to IEEE 1687 instruments. | Michele Portolan |
| 2016 | IOLTS | Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. | K. Chibani, Michele Portolan, Rgis Leveugle |
| 2016 | ITC | Accessing 1687 systems using arbitrary protocols. | Michele Portolan |
| 2015 | VTS | Special session 8C: E.J. McCluskey doctoral thesis award semi-final. | Michele Portolan, K. Huang |
| 2014 | VTS | Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-final. | Michele Portolan, Michail Maniatakos |
| 2013 | VTS | Special session 8A: E.J. McCluskey doctoral thesis award semi-final - presentations. | Michele Portolan, Michail Maniatakos |
| 2013 | VTS | Special session 3B: E.J. McCluskey Doctoral Thesis Award semi-final - Posters. | Michele Portolan, Michail Maniatakos |
| 2013 | WiOpt | Automatic equivalent model generation and evolution for small cell networks. | Davide Cherubini, Michele Portolan |
| 2012 | ITC | Packet-based JTAG for remote testing. | Michele Portolan |
| 2010 | ITC | Scan chain securization though Open-Circuit Deadlocks. | Michele Portolan, Bradford G. Van Treuren, Suresh Goyal |
| 2009 | ITC | Scalable and efficient integrated test architecture. | Michele Portolan, Suresh Goyal, Bradford G. Van Treuren |
| 2008 | ITC | A New Language Approach for IJTAG. | Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook |
| 2005 | EUC | Towards a Secure and Reliable System. | Michele Portolan, Rgis Leveugle |
| 2005 | IOLTS | On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. | Michele Portolan, Rgis Leveugle |
| 2004 | IOLTS | Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. | Michele Portolan, Rgis Leveugle |