Mohammad Hosseinabady
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
20
Venues
9
Active years
2005–2018
Best venue rank
B
Where they publish
Papers
20 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | DATE | Multi-precision convolutional neural networks on heterogeneous hardware. | Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, Jos L. Nez-Yez |
| 2018 | FPL | Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. | Sam Amiri, Mohammad Hosseinabady, Andrs Rodrguez, Rafael Asenjo, Angeles G. Navarro, Jos L. Nez-Yez |
| 2017 | FPL | A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. | Mohammad Hosseinabady, Jos Luis Nez-Yez |
| 2015 | FPL | Energy optimization of FPGA-based stream-oriented computing with power gating. | Mohammad Hosseinabady, Jos Luis Nez-Yez |
| 2015 | FPL | Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. | Mohammad Hosseinabady, Jos Luis Nez-Yez |
| 2014 | FPL | Run-time power gating in hybrid ARM-FPGA devices. | Mohammad Hosseinabady, Jos Luis Nez-Yez |
| 2010 | FDL | SystemC Architectural Transaction Level Modelling for Large NoCs. | Mohammad Hosseinabady, Jos L. Nez-Yez |
| 2010 | ISCAS | Effective modelling of large NoCs using SystemC. | Mohammad Hosseinabady, Jos L. Nez-Yez |
| 2009 | FPL | Run-time resource management in fault-tolerant network on reconfigurable chips. | Mohammad Hosseinabady, Jos L. Nez-Yez |
| 2008 | DATE | De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
| 2008 | ISCAS | Fault tolerant bit parallel finite field multipliers using LDPC codes. | Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan |
| 2007 | CIT | Single Event Upset Detection and Correction. | Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan |
| 2007 | DATE | Using the inter- and intra-switch regularity in NoC switch testing. | Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi |
| 2007 | IOLTS | An Analytical Model for Reliability Evaluation of NoC Architectures. | Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi |
| 2007 | IOLTS | Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale |
| 2007 | VTS | A UML Based System Level Failure Rate Assessment Technique for SoC Designs. | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi |
| 2006 | DATE | A concurrent testing method for NoC switches. | Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi |
| 2006 | ETS | Single-Event Upset Analysis and Protection in High Speed Circuits. | Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto |
| 2005 | ASPDAC | TED+: a data structure for microprocessor verification. | Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi |
| 2005 | DATE | Simultaneous Reduction of Dynamic and Static Power in Scan Structures. | Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi |