| 2013 | FPGA | Improving bitstream compression by modifying FPGA architecture. | Seyyed Ahmad Razavi, Morteza Saheb Zamani |
| 2012 | DSD | Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins. | Somayeh Kashi, Morteza Saheb Zamani |
| 2012 | DSD | OWQS: One-Way Quantum Computation Simulator. | Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi |
| 2012 | FPGA | Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only). | Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani |
| 2011 | DSD | VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs. | Behzad Salami, Morteza Saheb Zamani, Ali Jahanian |
| 2010 | ASPDAC | Rule-based optimization of reversible circuits. | Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani |
| 2010 | ASPDAC | A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. | Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi |
| 2009 | ASPDAC | A cycle-based synthesis algorithm for reversible logic. | Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani |
| 2009 | DATE | Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. | Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani |
| 2009 | DSD | Improving Latency of Quantum Circuits by Gate Exchanging. | Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi |
| 2008 | AICCSA | Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. | Arash Mehdizadeh, Morteza Saheb Zamani |
| 2008 | ASPDAC | Design space exploration for a coarse grain accelerator. | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami |
| 2008 | ASPDAC | Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi |
| 2008 | CSICC | Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability. | Ali Jahanian, Morteza Saheb Zamani, Mostafa Rezvani, Mehrdad Najibi |
| 2008 | CSICC | A Novel Crosstalk Estimator after Placement. | Arash Mehdizadeh, Morteza Saheb Zamani |
| 2008 | DSD | A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. | Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi |
| 2008 | DSD | Performance and Timing Yield Enhancement using Highway-on-Chip Planning. | Ali Jahanian, Morteza Saheb Zamani |
| 2008 | DSD | Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. | Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi |
| 2008 | DSD | Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. | Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani |
| 2008 | DSD | An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. | Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi |
| 2007 | DSD | Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi |
| 2007 | ICCAD | A novel synthesis algorithm for reversible circuits. | Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani |
| 2006 | EUC | Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi |
| 2006 | FPL | A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. | Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani |
| 2005 | DSD | Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi |
| 2005 | FCCM | Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. | Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi |
| 2003 | IJCNN | Rectilinear floorplanning of FPGAs using Kohonen map. | Morteza Saheb Zamani, Masoud Soleimani |
| 1999 | IJCNN | An efficient method for placement of VLSI designs with Kohonen map. | Morteza Saheb Zamani, Farhad Mehdipour |
| 1995 | ASPDAC | A neural network approach to the placement problem. | Morteza Saheb Zamani, Graham R. Hellestrand |
| 1995 | ISCAS | A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. | Morteza Saheb Zamani, Graham R. Hellestrand |
| 1995 | IWANN | A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. | Morteza Saheb Zamani, Graham R. Hellestrand |