Murali Jayapala
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
7
Active years
2001–2009
Best venue rank
B
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | ASPDAC | Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. | Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2009 | DSD | Compilation Technique for Loop Overhead Minimization. | Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris |
| 2008 | VLSID | Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. | Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest |
| 2007 | DATE | Very wide register: an asymmetric register file organization for low power embedded processors. | Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal |
| 2006 | DATE | Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. | Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest |
| 2004 | ASPDAC | Instruction buffering exploration for low energy VLIWs with instruction clusters. | Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal |
| 2004 | SAC | L0 buffer energy optimization through scheduling and exploration. | Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal |
| 2004 | RTSS | Design Style Case Study for Embedded Multi Media Compute Nodes. | Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frdric Robert, Jordi Carrabina Bordoll |
| 2003 | FPL | Low Power Coarse-Grained Reconfigurable Instruction Set Processor. | Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal |
| 2002 | VLSID | Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. | Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck |
| 2001 | FPL | CRISP: A Template for Reconfigurable Instruction Set Processors. | Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins |