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N. Pete Sedcole

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

13

Venues

4

Active years

2003–2010

Best venue rank

B

Where they publish

Papers

13 indexed papers, newest first.

YearVenueTitleAuthors
2010FPGADegradation in FPGAs: measurement and modelling.Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2009FPLCompensating for variability in FPGAs by re-mapping and re-placement.N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung
2009ISCASThroughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung
2008FPGAHigh-throughput interconnect wave-pipelining for global communication in FPGAs.Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008FPGAMeasuring and modeling FPGA clock variability.N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008FPLFault tolerant methods for reliability in FPGAs.Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
2008FPLCombating process variation on FPGAS with a precise at-speed delay measurement method.Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole
2007FPGAParametric yield in FPGAs due to within-die delay variations: a quantitative analysis.N. Pete Sedcole, Peter Y. K. Cheung
2006FPLOn-FPGA Communication Architectures and Design Factors.Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2005FPLModular Partial Reconfiguration in Virtex FPGAs.N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght
2004FCCMA Structured System Methodology for FPGA Based System-on-A-Chip Design.N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2004FPLA Structured Methodology for System-on-an-FPGA Design.N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2003FPLA Reconfigurable Platform for Real-Time Embedded Video Image Processing.N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk