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Narendra V. Shenoy

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

26

Venues

5

Active years

1990–2007

Best venue rank

A*

Where they publish

Papers

26 indexed papers, newest first.

YearVenueTitleAuthors
2007VLSIDImpact of Modern Process Technologies on the Electrical Parameters of Interconnects.Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
2005ICCADStatistical gate sizing for timing yield optimization.Debjit Sinha, Narendra V. Shenoy, Hai Zhou
2004DACDesign automation for mask programmable fabrics.Narendra V. Shenoy, Jamil Kawa, Raul Camposano
2004VLSIDComputing Silent Gate Models for Noise Analysis from Slew and Delay Tables.Shabbir H. Batterywala, Narendra V. Shenoy
2003DACEmerging markets: design goes global.Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei
2003VLSIDA Method to Estimate Slew and Delay in Coupled Digital Circuits.Shabbir H. Batterywala, Narendra V. Shenoy
2002DACAn efficient routing database.Narendra V. Shenoy, William Nicholls
2002ICCADTrack assignment: a desirable intermediate step between global routing and detailed routing.Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
2002ICCDAn Efficient External-Memory Implementation of Region Query with Application to Area Routing.Stan Y. Liao, Narendra V. Shenoy, William Nicholls
2001ASPDACEfficient minimum spanning tree construction without Delaunay triangulation.Hai Zhou, Narendra V. Shenoy, William Nicholls
2001DACTiming Analysis with Crosstalk as Fixpoints on Complete Lattice.Hai Zhou, Narendra V. Shenoy, William Nicholls
1999ICCDA Robust Solution to the Timing Convergence Problem in High-Performance Design.Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking
1997ICCDDiscrete Drive Selection for Continuous Sizing.Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
1996ICCADEmbedded tutorial: Speed - new paradigms in design for performance.Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
1995VLSIDFunctional clock schedule optimization.Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994ICCADEfficient implementation of retiming.Narendra V. Shenoy, Richard L. Rudell
1993DACA Verification Technique for Gated Clock.Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli
1993DACResynthesis of Multi-Phase Pipelines.Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993ICCADMinimum padding to satisfy short path constraints.Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992DACOn the Temporal Equivalence of Sequential Circuits.Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992ICCADGraph algorithms for clock schedule optimization.Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992ICCADVerifying clock schedules.Thomas G. Szymanski, Narendra V. Shenoy
1991ICCADImproved Logic Synthesis Algorithms for Table Look Up Architectures.Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991ICCADPerformance Directed Synthesis for Table Look Up Programmable Gate Arrays.Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991ICCDRetiming of Circuits with Single Phase Transparent Latches.Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990DACLogic Synthesis for Programmable Gate Arrays.Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli