Nilanjan Mukherjee
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
60
Venues
7
Active years
1993–2025
Best venue rank
A*
Where they publish
Papers
60 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ITC | In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs. | Varun Sehgal, Subramanian Mahadevan, Ashrith S. Harith, Mohit Sharma, Saket Goyal, Nilanjan Mukherjee |
| 2025 | VTS | Timing-Verification Test Generation Targeting Small Delay Defects. | Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski |
| 2024 | ITC | Delay Monitoring Under Different PVT Corners for Test and Functional Operation. | Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2024 | ITC | Deterministic In-Fleet Scan Test for a Cloud Computing Platform. | Dan Trock, Subramanian Mahadevan, Nilanjan Mukherjee, Lee Harrison, Janusz Rajski, Jerzy Tyszer |
| 2024 | VLSID | X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology. | Ashrith S. Harith, Yingdi Liu, Nilanjan Mukherjee, Jeffrey Mayer |
| 2023 | IECON | An Approach to Battery Pack Balancing Control Optimizing the Usable Capacity of the Battery Pack. | Nilanjan Mukherjee, Sudeshna Sarkar |
| 2023 | ITC | A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. | Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee |
| 2023 | VTS | Innovation Practices Track: Silicon Lifecycle Management Challenges and Opportunities. | Fei Su, Xiankun Robert Jin, Nilanjan Mukherjee, Yervant Zorian |
| 2022 | ITC | Test Generation for an Iterative Design Flow with RTL Changes. | Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2022 | VTS | Fast Test Generation for Structurally Similar Circuits. | Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2022 | VTS | Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety. | Minqiang Peng, Youfa Wu, Jialiang Li, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutyunyan, Yervant Zorian, Nilanjan Mukherjee |
| 2020 | ETS | Test Sequence-Optimized BIST for Automotive Applications. | Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer |
| 2020 | ITC | X-Tolerant Tunable Compactor for In-System Test. | Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak |
| 2020 | VTS | Effective Design of Layout-Friendly EDT Decompressor. | Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer |
| 2019 | ITC | Test Time and Area Optimized BrST Scheme for Automotive ICs. | Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki |
| 2018 | ITC | Deterministic Stellar BIST for In-System Automotive Test. | Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer |
| 2017 | ITC | Full-scan LBIST with capture-per-cycle hybrid test points. | Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada |
| 2016 | ITC | Minimal area test points for deterministic patterns. | Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer |
| 2016 | ITC | Test point insertion in hybrid test compression/LBIST architectures. | Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada |
| 2016 | VLSID | Digital Testing of ICs for Automotive Applications. | Nilanjan Mukherjee, Janusz Rajski |
| 2015 | DAC | Design for low test pattern counts. | Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada |
| 2015 | ITC | Embedded deterministic test points for compact cell-aware tests. | Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada |
| 2015 | VTS | Innovative practices session 11C: Advanced scan methodologies [3 presentations]. | Janusz Rajski, Nilanjan Mukherjee |
| 2014 | DAC | On Using Implied Values in EDT-based Test Compression. | Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2014 | ITC | Isometric test compression with low toggling activity. | Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang |
| 2014 | VTS | Innovative practices session 1C: Existing/emerging low power techniques. | Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane |
| 2013 | ETS | New test compression scheme based on low power BIST. | Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2013 | ITC | EDT bandwidth management - Practical scenarios for large SoC designs. | Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles |
| 2012 | ITC | Low power programmable PRPG with enhanced fault coverage gradient. | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2011 | ETS | Reduced ATE Interface for High Test Data Compression. | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2011 | ITC | EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. | Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2010 | ITC | Low power compression of incompatible test cubes. | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer |
| 2010 | ITC | Dynamic channel allocation for higher EDT compression in SoC designs. | Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer |
| 2010 | ITC | Low capture power at-speed test in EDT environment. | Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab |
| 2009 | ITC | Compression based on deterministic vector clustering of incompatible test cubes. | Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer |
| 2009 | ITC | Fault diagnosis for embedded read-only memories. | Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2009 | VLSID | High-Speed On-Chip Event Counters for Embedded Systems. | Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2009 | VLSID | Defect Aware to Power Conscious Tests - The New DFT Landscape. | Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2009 | VTS | Highly X-Tolerant Selective Compaction of Test Responses. | Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer |
| 2008 | ITC | High Test Quality in Low Pin Count Applications. | Jayant D'Souza, Subramanian Mahadevan, Nilanjan Mukherjee, Graham Rhodes, Jocelyn Moreau, Thomas Droniou, Paul Armagnat, Damien Sartoretti |
| 2008 | ITC | High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. | Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2006 | ITC | X-Press Compactor for 1000x Reduction of Test Data. | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab |
| 2005 | ITC | Full-speed field-programmable memory BIST architecture. | Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy |
| 2005 | ITC | Chasing subtle embedded RAM defects for nanometer technologies. | Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee |
| 2004 | ITC | Cost of Test - Taking Control. | Nilanjan Mukherjee |
| 2004 | VLSID | At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. | Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee |
| 2004 | VLSID | Embedded Test for Low Cost Manufacturing. | Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht |
| 2004 | VTS | Planar High Performance Ring Generators. | Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2003 | ITC | Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. | Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski |
| 2002 | ITC | Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. | Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan |
| 2002 | ITC | Embedded Deterministic Test for Low-Cost Manufacturing Test. | Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian |
| 2002 | VLSID | Constraint Driven Pin Mapping for Concurrent SOC Testing. | Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy |
| 2001 | ITC | On RTL scan design. | Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy |
| 1998 | ITC | Versatile BIST: an integrated approach to on-line/off-line BIST. | Ramesh Karri, Nilanjan Mukherjee |
| 1998 | ITC | A BIST scheme for the detection of path-delay faults. | Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik |
| 1997 | ITC | Parameterizable Testing Scheme for FIR Filters. | Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 1995 | DAC | Software Accelerated Functional Fault Simulation for Data-Path Architectures. | Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 1995 | ICCAD | On testable multipliers for fixed-width data path architectures. | Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 1995 | VTS | Arithmetic built-in self test for high-level synthesis. | Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer |
| 1993 | VLSID | An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. | Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji |