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Oana Boncalo

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

18

Venues

5

Active years

2007–2020

Best venue rank

C

Where they publish

Papers

18 indexed papers, newest first.

YearVenueTitleAuthors
2020SACILayered LDPC decoder in-order message access scheduling: a case study.Oana Boncalo, Alexandru Amaricai
2019DSDConfigurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller.Oana Boncalo, Alexandru Amaricai, Zsfia Lendek
2018DSDMemory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding.Oana Boncalo, Alexandru Amaricai, Sergiu Nimara
2018ISCASLightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo
2016DDECSFPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization.Sergiu Nimara, Oana Boncalo, Alexandru Amaricai, Mircea Popa
2016DSDQC-LDPC Gear-Like Decoder Architecture with Multi-domain Quantization.Oana Boncalo
2015DDECSPerformance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques.Ioana Mot, Oana Boncalo, Alexandru Amaricai
2015SACIHardware support for performance measurements and energy estimation of OpenRISC processor.Lucian Bara, Oana Boncalo, Marius Marcu
2014DSDProbabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits.Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Jiaoyan Chen, Emanuel M. Popovici
2014FPLAn FPGA sliding window-based architecture harris corner detector.Alexandru Amaricai, Constantina-Elena Gavriliu, Oana Boncalo
2014FPLCost-efficient FPGA layered LDPC decoder with serial AP-LLR processing.Oana Boncalo, Alexandru Amaricai, Andrei Hera, Valentin Savin
2011SACIModels and implementations of hardware interface modules in a multi-processor system-on-chip simulator.Alexandru Amaricai, Alin Dobre, Oana Boncalo, Andrei V. Tanase, Camelia Valuch
2009DSDImproving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation.Alexandru Amaricai, Oana Boncalo
2009DSDReliability Analysis of Qubit Data Movement for Distributed Quantum Computation.Oana Boncalo, Alexandru Amaricai
2007DDECSDesign of Addition and Multiplication Units for High Performance Interval Arithmetic Processor.Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo
2007DSDExploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo
2007DSDSaboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment.Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai
2007SACISimulated Fault Injection for Quantum Circuits Based on Simulator Commands.Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai