| 2023 | AIME | Can Knowledge Transfer Techniques Compensate for the Limited Myocardial Infarction Data by Leveraging Hmodynamics? An in silico Study. | Riccardo Tenderini, Federico Betti, Ortal Yona Senouf, Olivier Muller, Simone Deparis, Annalisa Buffa, Emmanuel Abbe |
| 2021 | RSP | Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. | Bruno Ferres, Olivier Muller, Frdric Rousseau |
| 2020 | RSP | (System)Verilog to Chisel Translation for Faster Hardware Design. | Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Grolat, Frdric Ptrot |
| 2018 | RSP | Message-Oriented Devices on FPGAs. | Thomas Baumela, Olivier Gruber, Olivier Muller, Frdric Ptrot |
| 2017 | RSP | Prototyping dynamic task migration on heterogeneous reconfigurable systems. | Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frdric Rousseau |
| 2016 | DSD | HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. | Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Rgis Leveugle, Frdric Rousseau |
| 2016 | FPL | Demonstration of a context-switch method for heterogeneous reconfigurable systems. | Arief Wicaksana, Alban Bourge, Olivier Muller, Frdric Rousseau |
| 2016 | RSP | On-board non-regression test of HLS tools targeting FPGA. | Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Frdric Rousseau, Arif Sasongko |
| 2015 | FCCM | Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems. | Alban Bourge, Olivier Muller, Frdric Rousseau |
| 2015 | FPGA | A Novel Method for Enabling FPGA Context-Switch (Abstract Only). | Alban Bourge, Olivier Muller, Frdric Rousseau |
| 2013 | DSD | A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints. | Adrien Prost-Boucle, Olivier Muller, Frdric Rousseau |
| 2012 | FPL | HCM: An abstraction layer for seamless programming of DPR FPGA. | Yan Xu, Olivier Muller, Pierre-Henri Horrein, Frdric Ptrot |
| 2008 | RSP | From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. | Olivier Muller, Amer Baghdadi, Michel Jzquel |
| 2007 | DATE | Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. | Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jzquel |
| 2006 | DATE | ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. | Olivier Muller, Amer Baghdadi, Michel Jzquel |
| 2006 | GLOBECOM | On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. | Olivier Muller, Amer Baghdadi, Michel Jzquel |