| 2016 | ICCAD | Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks. | Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong |
| 2016 | ISLPED | Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper. | Jason Cong, Muhuan Huang, Peichen Pan, Di Wu, Peng Zhang |
| 1999 | DAC | Performance-Driven Integration of Retiming and Resynthesis. | Peichen Pan |
| 1999 | VLSID | Optimal Retiming for Initial State Computation. | Peichen Pan, Guohua Chen |
| 1999 | VLSID | The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. | Prashant Saxena, Peichen Pan, C. L. Liu |
| 1998 | FPGA | A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs. | Peichen Pan, Chih-Chang Lin |
| 1998 | ISLPED | Low power logic synthesis under a general delay model. | Unni Narayanan, Peichen Pan, C. L. Liu |
| 1997 | ICCD | Optimal Clock Period Clustering for Sequential Circuits with Retiming. | Arvind K. Karandikar, Peichen Pan, C. L. Liu |
| 1997 | ICCD | Continuous Retiming: Algorithms and Applications. | Peichen Pan |
| 1996 | DAC | Desensitization for Power Reduction in Sequential Circuits. | Xiangfeng Chen, Peichen Pan, C. L. Liu |
| 1996 | DAC | Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. | Peichen Pan, C. L. Liu |
| 1996 | FPGA | Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. | Peichen Pan, C. L. Liu |
| 1995 | DAC | Partial Scan with Pre-selected Scan Signals. | Peichen Pan, C. L. Liu |
| 1994 | ICCAD | Area minimization for hierarchical floorplans. | Peichen Pan, Weiping Shi, C. L. Liu |
| 1993 | DAC | Optimal Graph Constraint Reduction for Symbolic Layout Compaction. | Peichen Pan, Sai-keung Dong, C. L. Liu |
| 1992 | ICCAD | Area minimization for general floorplans. | Peichen Pan, C. L. Liu |