| 2025 | IPCCC | Gate-Breaker: An LLM-Powered Netlist-to-RTL Reverse Engineering Tool. | Md. Omar Faruque, Peter Jamieson, Ahmad Patooghy, Abdel-Hameed A. Badawy |
| 2024 | FIE | Pre-Conference Workshop: Let's Play- Improving our Teaching in the Medium of Board Games. | Peter Jamieson, Karen C. Davis, Eric J. Rapos |
| 2024 | IPCCC | The Seeker's Dilemma: Realistic Formulation and Benchmarking for Hardware Trojan Detection. | Amin Sarihi, Ahmad Patooghy, Abdel-Hameed A. Badawy, Peter Jamieson |
| 2023 | FIE | With ChatGPT, Do We have to Rewrite Our Learning Objectives - CASE Study in Cybersecurity. | Peter Jamieson, Suman Bhunia, Dhananjai M. Rao |
| 2021 | FIE | Personalizing Online Computer Engineering Resources and Labs for Digital, Embedded, and Computer System Courses. | Peter Jamieson, Ricardo S. Ferreira, Jos Augusto Miranda Nacif |
| 2021 | HCI | Lego | Alejandro Cabrerizo, Will Zeurcher, Thomas Wright, Peter Jamieson |
| 2021 | ISCAS | Is It Time to Include High-Level Synthesis Design in Digital System Education for Undergraduate Computer Engineers? | Isaac Nelson, Ricardo S. Ferreira, Jos Augusto Miranda Nacif, Peter Jamieson |
| 2020 | GECCO | GA-lapagos, an open-source c framework including a python-based system for data analysis. | Peter Jamieson, Ricardo S. Ferreira, Jos Augusto Miranda Nacif |
| 2017 | FIE | WIP - A modification to the case study method to teach students to read academic papers. | Peter Jamieson |
| 2016 | FIE | Improved method for creating criterion maps for automatic mind map analysis. | Amber Franklin, Ryan Sunderhaus, Chris Bell, Peter Jamieson |
| 2016 | FIE | A framework to help analyze if creating a game to teach a learning objective is worth the work. | Peter Jamieson, Lindsay D. Grace |
| 2015 | FIE | Evaluating metrics for automatic mind map assessment in various classes. | Amber Franklin, Tuo Li, Peter Jamieson, Julie Semlak, Walter Vanderbush |
| 2015 | FIE | More missing the Boat - Arduino, Raspberry Pi, and small prototyping boards and engineering education needs them. | Peter Jamieson, Jeff Herdtner |
| 2014 | FPGA | A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only). | Farnaz Gharibian, Lesley Shannon, Peter Jamieson |
| 2014 | FPL | Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data. | Farnaz Gharibian, Lesley Shannon, Peter Jamieson |
| 2013 | CEC | Supergenes in a genetic algorithm for heterogeneous FPGA placement. | Peter Jamieson, Farnaz Gharibian, Lesley Shannon |
| 2013 | FIE | More graph comparison techniques on mind maps to provide students with feedback. | Peter Jamieson |
| 2013 | HCI | Metaheuristic Entry Points for Harnessing Human Computation in Mainstream Games. | Peter Jamieson, Lindsay Grace, Jack Hall, Aditya Wibowo |
| 2012 | FIE | Using modern graph analysis techniques on mind maps to help quantify learning. | Peter Jamieson |
| 2012 | FPGA | The VTR project: architecture and CAD for FPGAs from verilog to routing. | Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson |
| 2011 | FIE | Early project based learning improvements via a "star trek engineering room" game framework, and competition. | Peter Jamieson |
| 2010 | FCCM | Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. | Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon |
| 2010 | FPL | Finding System-Level Information and Analyzing Its Correlation to FPGA Placement. | Farnaz Gharibian, Lesley Shannon, Peter Jamieson |
| 2009 | FCCM | Benchmarking Reconfigurable Architectures in the Mobile Domain. | Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitknen |
| 2009 | FPGA | VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. | Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose |
| 2008 | FPL | Towards benchmarking energy efficiency of reconfigurable architectures. | Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa |
| 2005 | FPL | A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. | Peter Jamieson, Jonathan Rose |
| 2002 | HPCA | CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters. | Peter Jamieson, Angelos Bilas |