Po-Tsang Huang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
16
Venues
5
Active years
2006–2026
Best venue rank
C
Where they publish
Papers
16 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | Energy-Efficient All-Digital Computation-in-Memory Macro Design with CFeFET-based Booth Decoder. | Ting-Wei Yang, Wei Lu, Yuan-Yu Huang, Pin Su, Po-Tsang Huang |
| 2026 | VTS | Defect-based Testing for SRAM Address Decoders. | Ho-Jie Hsu, Hsien-Chen Lee, Chun-Yu Shen, Po-Tsang Huang, Shih-Chieh Lin, Yung-Jheng Wang, Ying-Yen Chen, Chien-Yuan Pao, Hung-Yu Lee, Mango Chia-Tso Chao |
| 2025 | ISCAS | Irregular Operation-Unit-based Compression for Non-Volatile Computation-in-Memory Accelerator. | Liang-Te Huang, Wei Lu, Hung-Ming Chen, Po-Tsang Huang |
| 2024 | ISCAS | A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning. | Wei Lu, Han-Hsiang Pei, Jheng-Rong Yu, Hung-Ming Chen, Po-Tsang Huang |
| 2018 | FCCM | SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing. | Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu |
| 2018 | FPL | SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing. | Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu |
| 2017 | ISCAS | Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. | Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang |
| 2017 | ISCAS | An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. | Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou |
| 2016 | FCCM | The SMEM Seeding Acceleration for DNA Sequence Alignment. | Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu |
| 2016 | ISCAS | An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. | Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou |
| 2014 | ISCAS | Energy-efficient configurable discrete wavelet transform for neural sensing applications. | Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang |
| 2012 | ISCAS | Substrate noise suppression technique for power integrity of TSV 3D integration. | Po-Jen Yang, Po-Tsang Huang, Wei Hwang |
| 2010 | ICMLC | A decision support system of statistical process control for printed circuit boards manufacturing. | Hsin Rau, Chien-Hung Wu, Wei-Jung Shiang, Po-Tsang Huang |
| 2008 | ISCAS | A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. | Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang |
| 2008 | ISCAS | "Green" micro-architecture and circuit co-design for ternary content addressable memory. | Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang |
| 2006 | ISCAS | 2-level FIFO architecture design for switch fabrics in network-on-chip. | Po-Tsang Huang, Wei Hwang |