Prakash Narayanan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
4
Active years
2011–2017
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | VTS | An optimised SDD ATPG and SDQL computation method across different pattern sets. | Wilson Pradeep, Prakash Narayanan, Rubin A. Parekhji |
| 2014 | IOLTS | Novel self-test methods to reduce on-chip memory requirements and improved test coverage. | Prakash Narayanan, Satish Ravichandran, Balaji Ramayanam |
| 2011 | DATE | Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system. | Lakshmanan Balasubramanian, Puneet Sabbarwal, Rajesh Kumar Mittal, Prakash Narayanan, Ranjit Kumar Dash, Anand Devendra Kudari, Srikanth Manian, Sudhir Polarouthu, Harikrishna Parthasarathy, Ravi C. Vijayaraghavan, Sachin Turkewadikar |
| 2011 | ITC | DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. | Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji |
| 2011 | VTS | Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. | Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal |