| 1999 | VLSID | Characterizing Individual Gate Power Sensitivity in Low Power Design. | Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy |
| 1998 | ASPDAC | Considering Testability during High-level Design (Embedded Tutorial). | Sujit Dey, Anand Raghunathan, Rabindra K. Roy |
| 1998 | VLSID | Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits. | Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee |
| 1998 | VLSID | Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. | Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey |
| 1997 | VLSID | Impact of Partial Reset on Fault Independent Testing and BIST. | Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy |
| 1997 | VLSID | T5: Low-Power Design. | Kaushik Roy, Rabindra K. Roy, Ramesh Harjani, K. S. Murthy |
| 1996 | VLSID | Synchronous Test Generation Model for Asynchronous Circuits. | Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy |
| 1995 | ASPDAC | Synthesis-for-testability using transformations. | Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy |
| 1995 | ITC | Advantages of High-Level Test Synthesis over Design for Test. | Rabindra K. Roy |
| 1994 | ICASSP | Behavioral synthesis of low-cost partial scan designs for DSP applications. | Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy |
| 1994 | ICCD | Initialization Isuues in the Synthesis of Asynchronous Circuits. | Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan |
| 1994 | VLSID | Synthesis of Initializable Asynchronous Circuits. | Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan |
| 1994 | VLSID | Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. | Abhijit Chatterjee, Rabindra K. Roy |
| 1994 | VTS | Design for diagnosability of linear digital filters using time-space expansion. | Abhijit Chatterjee, Rabindra K. Roy |
| 1994 | VTS | Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application. | Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy |
| 1993 | DAC | An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. | Abhijit Chatterjee, Rabindra K. Roy |
| 1993 | ICCAD | Exploiting hardware sharing in high-level synthesis for partial scan optimization. | Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy |
| 1993 | ICCD | Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. | Abhijit Chatterjee, Rabindra K. Roy |
| 1993 | VLSID | Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. | Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu |
| 1992 | ICCAD | Automatic test generation for linear digital systems with bi-level search using matrix transform methods. | Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu |
| 1992 | VTS | Delay fault testing of iterative arithmetic arrays. | Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu |
| 1991 | ITC | The Best Flip-Flops to Scan. | Miron Abramovici, James J. Kulikowski, Rabindra K. Roy |
| 1989 | ICCAD | Dynamic redundancy identification in automatic test generation. | Miron Abramovici, David T. Miller, Rabindra K. Roy |
| 1988 | DAC | Fault Simulation in a Distributed Environment. | Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers |
| 1988 | ICCAD | Compaction of ATPG-generated test sequences for sequential circuits. | Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh |