| 2008 | VLSID | A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
| 2001 | VLSID | Timing Verification and Delay Test Generation for Hierarchical Designs. | Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri |
| 2000 | VLSID | Hierarchical Test Generation for Systems On a Chip. | Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab |
| 1999 | DAC | Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. | Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham |
| 1997 | ITC | A Novel Functional Test Generation Method for Processors Using Commercial ATPG. | Raghuram S. Tupuri, Jacob A. Abraham |
| 1997 | VLSID | A Novel Hierarchical Test Generation Method for Processors. | Raghuram S. Tupuri, Jacob A. Abraham |
| 1992 | VLSID | Design Migration Across Technology - Making It Work. | Soumitra De Sirkar, Raghuram S. Tupuri, C. Sudha Madhuri, G. Rajagopalan, Kalpesh D. Mehta, C. G. Madhukar, Giridhar Bajpe |