| 2018 | DATE | SAT-based redundancy removal. | Krishanu Debnath, Rajeev Murgai, Mayank Jain, Janet Olson |
| 2008 | DATE | Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. | Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng |
| 2007 | ICCD | Fast power network analysis with multiple clock domains. | Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng |
| 2007 | VLSID | An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. | Vineet Wason, Rajeev Murgai, William W. Walker |
| 2006 | DATE | Analyzing timing uncertainty in mesh-based clock architectures. | Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai |
| 2006 | VLSID | Accurate Substrate Noise Analysis Based on Library Module Characterization. | Subodh M. Reddy, Rajeev Murgai |
| 2005 | ICCAD | A sliding window scheme for accurate clock mesh analysis. | Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai |
| 2005 | VLSID | Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. | Rajeev Murgai |
| 2004 | DATE | Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. | Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori |
| 2004 | DATE | Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction. | Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury |
| 2004 | ICCD | XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. | Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma |
| 2004 | ISCAS | Macromodeling of digital libraries for substrate noise analysis. | Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury |
| 2004 | VLSID | Net Buffering in the Presence of Multiple Timing Views. | Rajeev Murgai |
| 2002 | VLSID | Layout-Driven Timing Optimization by Generalized De Morgan Transform. | Supratik Chakraborty, Rajeev Murgai |
| 2001 | ASPDAC | Efficient global fanout optimization algorithms. | Rajeev Murgai |
| 2001 | VLSID | Complexity Of Minimum-Delay Gate Resizing. | Supratik Chakraborty, Rajeev Murgai |
| 2000 | ICCAD | Layout-Driven Area-Constrained Timing Optimization by Net Buffering. | Rajeev Murgai |
| 2000 | ICCAD | An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. | Arlindo L. Oliveira, Rajeev Murgai |
| 2000 | VLSID | Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization. | Rajeev Murgai |
| 1999 | DATE | On Reducing Transitions Through Data Modifications. | Rajeev Murgai, Masahiro Fujita |
| 1999 | ICCAD | Performance optimization under rise and fall parameters. | Rajeev Murgai |
| 1999 | ICCAD | On the global fanout optimization problem. | Rajeev Murgai |
| 1999 | VLSID | Efficient Scheduling Techniques for ROBDD Construction. | Rajeev Murgai, Jawahar Jain, Masahiro Fujita |
| 1998 | DAC | Using Complementation and Resequencing to Minimize Transitions. | Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira |
| 1997 | ICCAD | Speeding up technology-independent timing optimization by network partitioning. | Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita |
| 1997 | VLSID | Some Recent Advances in Software and Hardware Logic Simulation. | Rajeev Murgai, Masahiro Fujita |
| 1995 | DATE | Decomposition of logic functions for minimum transition activity. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | ICCD | Logic synthesis for a single large look-up table. | Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose |
| 1994 | DAC | Optimum Functional Decomposition Using Encoding. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | DAC | Sequential Synthesis for Table Look Up Programmable Gate Arrays. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | ICCAD | Cube-packing and two-level minimization. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | ICCD | Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | DAC | An Improved Synthesis Algorithm for Multiplexor-Based PGA's. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCAD | On Clustering for Minimum Delay/Area. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCAD | Improved Logic Synthesis Algorithms for Table Look Up Architectures. | Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCAD | Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. | Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | DAC | Logic Synthesis for Programmable Gate Arrays. | Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1989 | ICCAD | SLIP: a software environment for system level interactive partitioning. | Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton |