Rajesh Galivanche
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
6
Active years
1989–2010
Best venue rank
A*
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | DAC | Bridging pre-silicon verification and post-silicon validation. | Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor |
| 2010 | ITC | Path coverage based functional test generation for processor marginality validation. | Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche |
| 2008 | DATE | A low-cost concurrent error detection technique for processor control logic. | Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche |
| 2008 | ETS | Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. | Cecilia Metra, Daniele Rossi, Martin Omaa, Abhijit Jas, Rajesh Galivanche |
| 2007 | DATE | Testing in the year 2020. | Rajesh Galivanche, Rohit Kapur, Antonio Rubio |
| 2006 | VTS | Session Abstract. | Rajesh Galivanche, Bob Gottlieb |
| 2005 | ITC | Is the concern for soft-error overblown? | Rajesh Galivanche |
| 2004 | ITC | Trends in manufacturing test methods and their implications. | Sandip Kundu, T. M. Mak, Rajesh Galivanche |
| 2003 | DATE | Circuit and Platform Design Challenges in Technologies beyond 90nm. | Bill Grundmann, Rajesh Galivanche, Sandip Kundu |
| 2000 | ETS | Test challenges in nanometer technologies. | Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche |
| 1989 | ICCD | An automatic test pattern generation program for large ASICs. | Dick L. Liu, Rajesh Galivanche, Charlie C. Hsu |