| 2018 | VTS | Innovative practices on memory test practice. | M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla |
| 2014 | VTS | Innovative practices session 1C: Existing/emerging low power techniques. | Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane |
| 2013 | VTS | Innovative practices session 2C: Memory test. | Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene |
| 2006 | VLSID | An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules. | Ramesh C. Tekumalla |
| 2003 | ITC | On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures. | Ramesh C. Tekumalla |
| 2002 | ITC | On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis. | Ramesh C. Tekumalla, Scott Davidson |
| 2001 | VTS | On Diagnosing Path Delay Faults in an At-Speed Environment. | Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar |
| 2000 | VTS | On Test Set Generation for Efficient Path Delay Fault Diagnosis. | Ramesh C. Tekumalla |
| 1999 | ITC | Robust testability of primitive faults using test points. | Ramesh C. Tekumalla, Premachandran R. Menon |
| 1998 | ICCAD | On primitive fault test generation in non-scan sequential circuits. | Ramesh C. Tekumalla, Premachandran R. Menon |
| 1997 | ICCAD | Test generation for primitive path delay faults in combinational circuits. | Ramesh C. Tekumalla, Premachandran R. Menon |
| 1997 | ICCD | Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. | Ramesh C. Tekumalla, Premachandran R. Menon |
| 1997 | ITC | Delay Testing with Clock Control: An Alternative to Enhanced Scan. | Ramesh C. Tekumalla, Premachandran R. Menon |
| 1996 | VLSID | Identifying Redundant Path Delay Faults in Sequential Circuits. | Ramesh C. Tekumalla, Premachandran R. Menon |