Ravindranath Naiknaware
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
1993–1999
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1999 | ISCAS | Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. | Ravindranath Naiknaware, Terri S. Fiez |
| 1999 | ISCAS | Switched-capacitor integrator design optimizing for power and process variations. | Ravindranath Naiknaware, Terri S. Fiez |
| 1998 | ICCAD | CMOS analog circuit stack generation with matching constraints. | Ravindranath Naiknaware, Terri S. Fiez |
| 1993 | ICCD | Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment. | Ravindranath Naiknaware |
| 1993 | ITC | Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. | Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa |
| 1993 | VLSID | Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. | Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin |