| 2020 | FCCM | Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme. | Sunwoong Kim, Keewoo Lee, Wonhee Cho, Yujin Nam, Jung Hee Cheon, Rob A. Rutenbar |
| 2020 | FPGA | Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL. | Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar |
| 2019 | FCCM | FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs. | Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei |
| 2019 | FPGA | A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference. | Tianqi Gao, Rob A. Rutenbar |
| 2019 | FPL | Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling. | Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei |
| 2018 | FCCM | Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA. | Sunwoong Kim, Rob A. Rutenbar |
| 2017 | FPL | Toward a pixel-parallel architecture for graph cuts inference on FPGA. | Tianqi Gao, Jungwook Choi, Shang-nien Tsai, Rob A. Rutenbar |
| 2017 | ICASSP | A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference. | Glenn G. Ko, Rob A. Rutenbar |
| 2016 | FPL | Configurable and scalable belief propagation accelerator for computer vision. | Jungwook Choi, Rob A. Rutenbar |
| 2016 | ICASSP | Analysis of error resiliency of belief propagation in computer vision. | Jungwook Choi, Ameya D. Patil, Rob A. Rutenbar, Naresh R. Shanbhag |
| 2016 | ITC | Keynote address Wednesday: Hardware inference accelerators for machine learning. | Rob A. Rutenbar |
| 2015 | FPL | Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. | Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, Jos F. Martnez, Rob A. Rutenbar |
| 2014 | AISTATS | Efficiently Enforcing Diversity in Multi-Output Structured Prediction. | Abner Guzmn-Rivera, Pushmeet Kohli, Dhruv Batra, Rob A. Rutenbar |
| 2014 | DAC | The First EDA MOOC: Teaching Design Automation to Planet Earth. | Rob A. Rutenbar |
| 2014 | ICASSP | A robust message passing based stereo matching kernel via system-level error resiliency. | Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar |
| 2013 | DAC | Automatic clustering of wafer spatial signatures. | Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar |
| 2013 | FPGA | Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform. | Jungwook Choi, Rob A. Rutenbar |
| 2013 | ISPASS | EMERALD: Characterization of emerging applications and algorithms for low-power devices. | Chuanjun Zhang, Glenn G. Ko, Jungwook Choi, Shang-nien Tsai, Minje Kim, Abner Guzmn-Rivera, Rob A. Rutenbar, Paris Smaragdis, Mi Sun Park, Vijaykrishnan Narayanan, Hongyi Xin, Onur Mutlu, Bin Li, Li Zhao, Mei Chen |
| 2013 | MEMOCODE | FPGA acceleration of Markov Random Field TRW-S inference for stereo matching. | Jungwook Choi, Rob A. Rutenbar |
| 2012 | FPL | Hardware implementation of MRF map inference on an FPGA platform. | Jungwook Choi, Rob A. Rutenbar |
| 2011 | ICCAD | Toward efficient spatial variation decomposition via sparse regression. | Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Rob A. Rutenbar |
| 2010 | DAC | Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. | Wangyang Zhang, Xin Li, Rob A. Rutenbar |
| 2010 | ICCAD | Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation. | Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar |
| 2009 | DAC | Oil fields, hedge funds, and drugs. | Patrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen |
| 2009 | FPGA | A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. | Edward C. Lin, Rob A. Rutenbar |
| 2009 | ICCAD | Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. | Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton |
| 2009 | Interspeech | Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis. | Kai Yu, Rob A. Rutenbar |
| 2008 | DAC | Verifying really complex systems: on earth and beyond. | Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman |
| 2008 | DATE | Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. | Amith Singhee, Sonia Singhal, Rob A. Rutenbar |
| 2008 | ICCAD | Practical, fast Monte Carlo statistical static timing analysis: why and how. | Amith Singhee, Sonia Singhal, Rob A. Rutenbar |
| 2008 | Interspeech | A low-power hardware search architecture for speech recognition. | Patrick J. Bourke, Rob A. Rutenbar |
| 2008 | VLSID | Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. | Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar |
| 2007 | ASPDAC | Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains. | Rob A. Rutenbar |
| 2007 | DAC | Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. | Amith Singhee, Rob A. Rutenbar |
| 2007 | DATE | Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. | Amith Singhee, Rob A. Rutenbar |
| 2007 | FPGA | A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. | Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen |
| 2007 | Interspeech | Generating small, accurate acoustic models with a modified Bayesian information criterion. | Kai Yu, Rob A. Rutenbar |
| 2006 | DAC | Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. | Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar |
| 2006 | DAC | Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. | Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar |
| 2006 | DATE | Verifying analog oscillator circuits using forward/backward abstraction refinement. | Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar |
| 2006 | ICCAD | Design automation for analog: the next generation of tool challenges. | Rob A. Rutenbar |
| 2006 | ICCAD | Faster, parametric trajectory-based macromodels via localized linear reductions. | Saurabh K. Tiwary, Rob A. Rutenbar |
| 2006 | Interspeech | Moving speech recognition from software to silicon: the in silico vox project. | Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen |
| 2005 | DAC | Scalable trajectory methods for on-demand analog macromodel extraction. | Saurabh K. Tiwary, Rob A. Rutenbar |
| 2005 | DAC | Timing-driven placement by grid-warping. | Zhong Xiu, Rob A. Rutenbar |
| 2005 | DATE | Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. | Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee |
| 2005 | ICCAD | Interval-valued statistical modeling of oxide chemical-mechanical polishing. | James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning |
| 2004 | DAC | Will Moore's Law rule in the land of analog? | Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Meng, Ernesto Perea, Robert Pitts, Charles G. Sodini, Jim Wieser |
| 2004 | DAC | Large-scale placement by grid-warping. | Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar |
| 2004 | DAC | A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. | Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley |
| 2004 | ICCAD | Towards formal verification of analog designs. | Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar |
| 2004 | ICCAD | Interval-valued reduced order statistical interconnect modeling. | James D. Ma, Rob A. Rutenbar |
| 2004 | ICCAD | Static statistical timing analysis for latch-based pipeline designs. | Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu |
| 2003 | DAC | Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. | Claire Fang Fang, Rob A. Rutenbar, Markus Pschel, Tsuhan Chen |
| 2003 | DAC | Mixed signals on mixed-signal: the right next technology. | Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Meng, Reza Rofougaran, James Spoto |
| 2003 | ICASSP | Floating-point error analysis based on affine arithmetic. | Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar |
| 2003 | ICCAD | Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. | Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen |
| 2002 | DAC | Remembrance of circuits past: macromodeling by data mining in large analog design spaces. | Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley |
| 2002 | FPL | Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar |
| 2002 | ICASSP | Floating-point bit-width optimization for low-power signal processing applications. | Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar |
| 2001 | DAC | Panel: (When) Will FPGAs Kill ASICs? | Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen |
| 2001 | DATE | A boolean satisfiability-based incremental rerouting approach with application to FPGAs. | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar |
| 2001 | ICCAD | Direct Transistor-Level Layout for Digital Blocks. | Prakash Gopalakrishnan, Rob A. Rutenbar |
| 2001 | ICCAD | ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits. | Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley |
| 2001 | ICCAD | Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. | Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen |
| 2001 | ICCAD | Automatic Hierarchical Design: Fantasy or Reality? (Panel). | Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jrgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni |
| 2001 | ISLPED | Low-power technology mapping for mixed-swing logic. | Rob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone |
| 2000 | DAC | Case studies: Chip design on the bleeding edge (panel session abstract). | John M. Cohn, Rob A. Rutenbar, Steve J. Young, Chris Malachowsky, Luis Aldaz |
| 2000 | DAC | Survival strategies for mixed-signal systems-on-chip (panel session). | Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy |
| 2000 | DAC | A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. | Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums |
| 2000 | DAC | Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). | Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow |
| 1999 | DAC | MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells. | Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley |
| 1999 | FPGA | Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar |
| 1999 | ISLPED | Inverse polarity techniques for high-speed/low-power multipliers. | Pascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley |
| 1999 | VLSID | Satisfiability-Based Detailed FPGA Routing. | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar |
| 1997 | FPGA | FPGA Routing and Routability Estimation via Boolean Satisfiability. | R. Glenn Wood, Rob A. Rutenbar |
| 1997 | ICCAD | A hierarchical decomposition methodology for multistage clock circuits. | Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar |
| 1996 | DAC | An | Blent Basaran, Rob A. Rutenbar |
| 1996 | DAC | Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. | L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen |
| 1995 | ICCAD | Performance-driven simultaneous place and route for island-style FPGAs. | Sudip K. Nag, Rob A. Rutenbar |
| 1995 | VLSID | Testability-oriented channel routing. | Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar |
| 1994 | DAC | Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. | Sudip Nag, Rob A. Rutenbar |
| 1994 | DAC | ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits. | Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley |
| 1994 | ICCAD | Synthesis of manufacturable analog circuits. | Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar |
| 1993 | ICCAD | Latchup-aware placement and parasitic-bounded routing of custom analog cells. | Blent Basaran, Rob A. Rutenbar, L. Richard Carley |
| 1992 | DAC | A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis. | Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar |
| 1992 | ICCAD | System-level routing of mixed-signal ASICs in WREN. | Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley |
| 1991 | ICCAD | Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II. | John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley |
| 1991 | ICCAD | A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. | Rajeev Jayaraman, Rob A. Rutenbar |
| 1990 | DAC | Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. | Erik C. Carlson, Rob A. Rutenbar |
| 1989 | DAC | Massively Parallel Switch-Level Simulation: A Feasibility Study. | Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar |
| 1989 | DAC | ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. | Dorothy E. Setliff, Rob A. Rutenbar |
| 1989 | ISCA | Logic Simulation on Massively Parallel Architectures. | Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar |
| 1988 | DAC | Mask Verification on the Connection Machine. | Erik C. Carlson, Rob A. Rutenbar |
| 1988 | ICCAD | Automatic layout of custom analog cells in ANAGRAM. | David J. Garrod, Rob A. Rutenbar, L. Richard Carley |
| 1988 | ICCAD | Analog circuit synthesis for performance in OASYS. | Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley |
| 1988 | ICCD | Analog circuit synthesis and exploration in OASYS. | Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley |
| 1987 | DAC | A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. | Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley |
| 1986 | DAC | Multiprocessor-based placement by simulated annealing. | Saul A. Kravitz, Rob A. Rutenbar |
| 1985 | DAC | Future directions for DA machine research (panel session). | Rob A. Rutenbar |
| 1982 | DAC | Cellular image processing techniques for VLSI circuit layout validation and routing. | Trevor N. Mudge, Rob A. Rutenbar, Robert M. Lougheed, Daniel E. Atkins |
| 1981 | ARITH | Case study of a VLSI design project: A simple inner product machine. | Rob A. Rutenbar, Y. E. Park |