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Romn Hermida

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

43

Venues

14

Active years

1996–2018

Best venue rank

A*

Where they publish

Papers

43 indexed papers, newest first.

YearVenueTitleAuthors
2018ASPDACLow-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks.Min Soo Kim, Alberto A. Del Barrio, Romn Hermida, Nader Bagherzadeh
2017DATEA slack-based approach to efficiently deploy radix 8 booth multipliers.Alberto A. Del Barrio, Romn Hermida
2013DATEMultispeculative additive trees in high-level synthesis.Alberto A. Del Barrio, Romn Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, Mara C. Molina
2013ICCDExploring the energy efficiency of Multispeculative Adders.Alberto A. Del Barrio, Romn Hermida, Seda Ogrenci Memik
2011DATEPower optimization in heterogenous datapaths.Alberto A. Del Barrio, Seda Ogrenci Memik, Mara C. Molina, Jos M. Mendas, Romn Hermida
2010DATEUsing Speculative Functional Units in high level synthesis.Alberto A. Del Barrio, Mara C. Molina, Jose Manuel Mendias, Romn Hermida, Seda Ogrenci Memik
2008DSDRestricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis.Alberto A. Del Barrio, Mara C. Molina, Jose Manuel Mendias, Esther Andres Perez, Romn Hermida
2008ICCDApplying speculation techniques to implement functional units.Alberto A. Del Barrio, Mara C. Molina, Jose Manuel Mendias, Esther Andres Perez, Romn Hermida, Francisco Tirado
2007DATEArea optimization of multi-cycle operators in high-level synthesis.Mara C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Romn Hermida
2006DATEPre-synthesis optimization of multiplications to improve circuit performance.Rafael Ruiz-Sautua, Mara C. Molina, Jos M. Mendas, Romn Hermida
2006FPLConfiguration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures.Fredy Rivera, Marcos Snchez-lez, Milagros Fernndez, Romn Hermida, Nader Bagherzadeh
2005ASPDACArrival time aware scheduling to minimize clock cycle length.Rafael Ruiz-Sautua, Mara C. Molina, Jos M. Mendas, Romn Hermida
2005DATEA Complete Network-On-Chip Emulation Framework.Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Romn Hermida, Francky Catthoor
2005DATEBehavioural Transformation to Improve Circuit Performance in High-Level Synthesis.Rafael Ruiz-Sautua, Mara C. Molina, Jos M. Mendas, Romn Hermida
2005ICCADPerformance-driven read-after-write dependencies softening in high-level synthesis.Rafael Ruiz-Sautua, Mara C. Molina, Jose Manuel Mendias, Romn Hermida
2005ISCASA novel approach for network on chip emulation.Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Romn Hermida, Francky Catthoor
2004DATEBehavioural Bitwise Scheduling Based on Computational Effort Balancing.Mara C. Molina, Rafael Ruiz-Sautua, Jos M. Mendas, Romn Hermida
2004PDPEmpirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays.Jos Manuel Colmenar, Oscar Garnica, Sonia Lpez, Jos Ignacio Hidalgo, Juan Lanchares, Romn Hermida
2003DATEHigh-Level Allocation to Minimize Internal Hardware Wastage.Mara C. Molina, Jos M. Mendas, Romn Hermida
2003DATELow Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures.Marcos Snchez-lez, Milagros Fernndez, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Romn Hermida
2003GECCOMulti-FPGA Systems Synthesis by Means of Evolutionary Computation.Jos Ignacio Hidalgo, Francisco Fernndez, Juan Lanchares, Juan Manuel Snchez-Prez, Romn Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica
2002DACHigh-level synthesis of multiple-precision circuitsindependent of data-objects length.Mara C. Molina, Jos M. Mendas, Romn Hermida
2002DATEMultiple-Precision Circuits Allocation Independent of Data-Objects Length.Mara C. Molina, Jos M. Mendas, Romn Hermida
2002DATEMaximizing Conditonal Reuse by Pre-Synthesis Transformations.Olga Pealba, Jos M. Mendas, Romn Hermida
2002DATEA Complete Data Scheduler for Multi-Context Reconfigurable Architectures.Marcos Snchez-lez, Milagros Fernndez, Rafael Maestre, Romn Hermida, Nader Bagherzadeh, Fadi J. Kurdahi
2002DATEFPGA Placement by Thermodynamic Combinatorial Optimization.Juan de Vicente, Juan Lanchares, Romn Hermida
2002DSDA Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design.Jos Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Romn Hermida
2002DSDOptimization of Equational Specifications Using Genetic Techniques.Aitor Ibarra, Jos M. Mendas, Juan Lanchares, Jos Ignacio Hidalgo, Romn Hermida
2002DSDEfficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis.Jos M. Mendas, Romn Hermida, Mara C. Molina, Olga Pealba
2002DSDBit-Level Allocation of Multiple-Precision Specifications.Mara C. Molina, Jos M. Mendas, Romn Hermida
2002DSDSource Code Transformation to Improve Conditional Hardware Reuse.Olga Pealba, Jos M. Mendas, Romn Hermida
2002EUROGPTransformation of Equational Specification by Means of Genetic Programming.Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, Jos Ignacio Hidalgo, Romn Hermida
2002ICCADBit-level scheduling of heterogeneous behavioural specifications.Mara C. Molina, Jos M. Mendas, Romn Hermida
2001DATEA pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits.Oscar Garnica, Juan Lanchares, Romn Hermida
2000FCCMOptimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.Rafael Maestre, Milagros Fernndez, Romn Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
2000ICCDOptimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.Rafael Maestre, Milagros Fernndez, Romn Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
2000RSPAdaptive FPGA Placement by Natural Optimization.Juan de Vicente, Juan Lanchares, Romn Hermida
1999DATEKernel Scheduling in Reconfigurable Computing.Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Romn Hermida, Milagros Fernndez
1999DATEThe Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach.Juan Antonio Maestro, Daniel Mozos, Romn Hermida
1999FPLPlacement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies.Juan de Vicente, Juan Lanchares, Romn Hermida
1998DATECorrect High-Level Synthesis: a Formal Perspective.Jos M. Mendas, Romn Hermida
1997VLSIDFormal Techniques for Hardware Allocation.Jos M. Mendas, Romn Hermida, Milagros Fernndez
1996DATEAlgebraic Support for Transformational Hardware Allocation.Jos M. Mendas, Romn Hermida, Milagros Fernndez