| 2017 | DATE | BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking. | Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee |
| 2017 | ITC | Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization. | Sabyasachi Deyati, Barry J. Muldrey, Byunghoo Jung, Abhijit Chatterjee |
| 2017 | VLSID | Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware. | Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee |
| 2016 | ITC | DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems. | Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee |
| 2016 | VLSID | TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm. | Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee |
| 2016 | VTS | Adaptive testing of analog/RF circuits using hardware extracted FSM models. | Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee |
| 2014 | ITC | A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time. | Bruce Querbach, Rahul Khanna, David Blankenbeckler, Yulan Zhang, Ronald T. Anderson, David G. Ellis, Zale T. Schoenborn, Sabyasachi Deyati, Patrick Chiang |
| 2014 | VTS | Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits. | Sabyasachi Deyati, Barry John Muldrey, Aritra Banerjee, Abhijit Chatterjee |
| 2013 | VLSID | VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests. | Sabyasachi Deyati, Aritra Banerjee, Barry John Muldrey, Abhijit Chatterjee |
| 2013 | VTS | RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning. | Barry John Muldrey, Sabyasachi Deyati, Michael Giardino, Abhijit Chatterjee |
| 2012 | ICCAD | Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits. | Abhijit Chatterjee, Sabyasachi Deyati, Barry John Muldrey, Shyam Kumar Devarakond, Aritra Banerjee |
| 2012 | IOLTS | Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis. | Sabyasachi Deyati, Aritra Banerjee, Abhijit Chatterjee |